Synchronous Sram; Clock Pins - Alpha Data ADM-XRC-II User Manual

5.7.

Synchronous SRAM

The four banks of synchronous SRAM are identical in device type and FPGA
interface. The devices fitted as pipelined ZBT parts organised as 256Kx32/36
bits each.
The pins are allocated to support synchronous burst or ZBT SRAM and each
bank provides the following interface.
FPGA Pin Active
high
RDn[36:0]
RAn[19:0] high
low
RCn[3:0]
RCn[4] low
low
RCn[5]
RCn[6] low
low
RCn[7]
RCn[8] low
Where n = 0,1,2,3,4,5. Therefore, SRAM 0 is controlled by the three bus ports
RD0[36:0], RA0[19:0] and RC0[8:0] and these are names used to constrain
the pins in the user constraints file or UCF.
5.8.

Clock pins

The six banks of SRAM are divided into two clock domains. Each SRAM clock
domain has its own pin routed from the FPGA.
ramclk[0]
ramclk[1]
ramclk_fb[0]
ramclk_fb[1]
Virtex II Device
ramclk[0]
to/from
Virtex DCM
ramclk_fb[0]
ramclk[1]
to/from
Virtex DCM
ramclk_fb[1]
Type Function
Bidir Data Bus
OUT Address Bus
OUT Byte enables
OUT Global write enable
OUT Chip enable
OUT ADV (advance) function
OUT Output enable
OUT CKE - clock enable
OUT Clock to SRAM 0, SRAM 1, SRAM 2
OUT Clock to SRAM 3, SRAM 4, SRAM 5
INPUT Clock feedback for ramclk[0]
INPUT Clock feedback for ramclk[1]
OBuf
IBufg
OBuf
IBufg
ADM-XRC-II User Manual
Clock Domain 0
Sram 0 Clk
Sram 1 Clk
Sram 2 Clk
Clock Domain 1
Sram 3 Clk
Sram 4 Clk
Sram 5 Clk
ADM-XRC-II User Manual
Version 1.5
Page 13