Configuring The Fpga; Selectmap Operation; Bitstream Issues - Alpha Data ADM-XRC-II User Manual

6.

Configuring the FPGA

The Virtex FPGA family support a mode of configuration referred to as
SelectMAP. The ADM-XRC-II uses the local bus clock to synchronise byte
loading through the SelectMAP interface and is thus limited to a maximum of
66Mbytes/sec.
6.1.

SelectMAP Operation

Before the FPGA can be configured using SelectMAP, the FPGA must be in a
state where it is ready to accept data. This can be confirmed by the following
process: -
1. Assert PROG and INIT, hold for 20 usec.
2. Release PROG and INIT, wait for 50usec
3. Check that INIT is not set.
If INIT is clear then configuration can proceed.
Configuration is a simple process and requires the entire bitstream to be
written to the SelectMAP register. At the end of the process, DONE should be
high. If DONE is not high and INIT is set then an error has occurred and will
probably be due to an invalid bitstream. Note that INIT is not valid when
DONE is set as it becomes a user I/O after configuration and is pulled low
(active) by default.
6.2.

Bitstream Issues

The bitstream produced by the bitgen program is stored in a design.bit file
and is suitable for use with the download cables produced by Xilinx. The
driver for the ADM-XRC-II loads this file and determines the location of the
binary bitstream data within it. This data is not suitable for writing directly to
the Selectman registers as it is bit reversed. The driver performs this bit
reversal on each byte before download to the FPGA.
Files generated by the promgen program and stored in mcs format for
example are not bit reversed but the resulting file is around three times larger
than the binary design.bit file.
ADM-XRC-II User Manual
ADM-XRC-II User Manual
Version 1.5
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