Direct Master Pci Remap Register; Dm Config/Io Register; Region 1 Descriptor; Runtime Registers - Alpha Data ADM-XRC-II User Manual

9.2.4. Direct Master PCI Remap Register

This register is for Local Bus initiated PCI Bus transactions (Direct Master)
and is not used in the ADM-XRC-II.

9.2.5. DM Config/IO Register

The DM (Direct Master) Config/IO register is used for controlling configuration
cycles on the PCI bus. It is not used in the ADM-XRC-II.

9.2.6. Region 1 Descriptor

The Region 1 Descriptor describes the attributes of Local Bus Space 1. It can
be seen that 8 bit local bus width is selected and that ready must be
generated by the target space. Burst transfers are not enabled in this space to
avoid any side effects of prefetching from control and /or FPGA configuration
registers.
Space 1 maps the flash memory, control registers and FPGA SelectMAP port.
Notes.
1. Do not enable burst for this region as it may cause side effects that will stop
FPGA loading and readback.
2. Internal wait states should always be 0.
3. Bus width is always 8 bit.

9.2.7. Runtime Registers

The runtime registers group together mailboxes, control and status registers.
The only registers applicable to the ADM-XRC-II in this group are the INTCSR
register at offset 68h and CNTRL at offset 6Ch.
It should be noted that Mailbox 0 and 1 can be set to initial values using the
EEPROM.

9.2.8. Interrupt Control/Status Register

In order to for a PCI host processor to receive interrupts from the many
sources in the PCI9656, the appropriate enable bits in the INTCSR must be
set.
Notes.
1. Refer to the PLX user manual for the actual register format.
2. Clearing a bit in this register does not remove the interrupting source, it
simply masks it.
ADM-XRC-II User Manual
ADM-XRC-II User Manual
Version 1.5
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