1.
Introduction ............................................................................................... 1
1.1.
Specifications .................................................................................... 1
2.
Installation................................................................................................. 2
2.1.
2.2.
2.3.
2.4.
3.
Board Overview ........................................................................................ 3
4.
PCI Bus Interface...................................................................................... 4
5.
5.1.
5.2.
5.2.1.
FCON Register ........................................................................... 6
5.2.2.
CCON Register........................................................................... 7
5.2.3.
ICON Registers .......................................................................... 8
5.2.4.
PSTAT Register.......................................................................... 8
5.2.5.
MODE Register .......................................................................... 9
5.2.6.
Flash_Page Register .................................................................. 9
5.2.7.
FPGA Operation .............................................................................................. 9
5.3.
Clock Distribution............................................................................... 9
5.4.
Input Clocks..................................................................................... 10
5.5.
Output Clocks .................................................................................. 11
5.6.
Local Bus......................................................................................... 12
5.7.
Synchronous SRAM ........................................................................ 13
5.8.
Clock pins ........................................................................................ 13
5.9.
5.9.1.
5.9.2.
5.10.
User I/O PMC Pn4 ....................................................................... 18
6.
Configuring the FPGA............................................................................. 19
6.1.
6.2.
Bitstream Issues .............................................................................. 19
7.
Interrupts ................................................................................................ 20
8.
Flash Memory ......................................................................................... 21
9.
9.1.
PCI Registers .................................................................................. 22
9.2.
9.2.1.
9.2.2.
9.2.3.
9.2.4.
9.2.5.
9.2.6.
9.2.7.
Runtime Registers .................................................................... 24
9.2.8.
9.2.9.
10.
EEPROM Contents ............................................................................. 26
Table of Contents
ADM-XRC-II User Manual
ADM-XRC-II User Manual
Version 1.5
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