Table Of Contents - Alpha Data ADM-XRC-II User Manual

1. Introduction ............................................................................................... 1
1.1. Specifications .................................................................................... 1
2. Installation................................................................................................. 2
2.1. Motherboard requirements ................................................................ 2
2.2. Handling instructions ......................................................................... 2
2.3. Installing the ADM-XRC-II onto a PMC motherboard ........................ 2
2.4. Installing the ADM-XRC-II if fitted to an ADC-PMC ........................... 2
3. Board Overview ........................................................................................ 3
4. PCI Bus Interface...................................................................................... 4
5. ADM-XRC-II Local Bus Architecture ......................................................... 5
5.1. Characteristics of Address Spaces .................................................... 5
5.2. Local Control Registers ..................................................................... 6
5.2.1. FCON Register ........................................................................... 6
5.2.2. CCON Register........................................................................... 7
5.2.3. ICON Registers .......................................................................... 8
5.2.4. PSTAT Register.......................................................................... 8
5.2.5. MODE Register .......................................................................... 9
5.2.6. Flash_Page Register .................................................................. 9
5.2.7. SelectMAP Register ................................................................... 9
FPGA Operation .............................................................................................. 9
5.3. Clock Distribution............................................................................... 9
5.4. Input Clocks..................................................................................... 10
5.5. Output Clocks .................................................................................. 11
5.6. Local Bus......................................................................................... 12
5.7. Synchronous SRAM ........................................................................ 13
5.8. Clock pins ........................................................................................ 13
5.9. User I/O Configuration ..................................................................... 14
5.9.1. User I/O XRM IO34 Front Panel Variant................................... 14
5.9.2. User I/O XRM IO146 Panel Variant .......................................... 15
5.10. User I/O PMC Pn4 ....................................................................... 18
6. Configuring the FPGA............................................................................. 19
6.1. SelectMAP Operation ...................................................................... 19
6.2. Bitstream Issues .............................................................................. 19
7. Interrupts ................................................................................................ 20
8. Flash Memory ......................................................................................... 21
9. PLX PCI9656 Initialisation ...................................................................... 22
9.1. PCI Registers .................................................................................. 22
9.2. Local Configuration Registers.......................................................... 23
9.2.1. Mode/Arbitration Register......................................................... 23
9.2.2. Big/Little Endian Descriptor Register ........................................ 23
9.2.3. Region 0 Descriptor.................................................................. 23
9.2.4. Direct Master PCI Remap Register .......................................... 24
9.2.5. DM Config/IO Register ............................................................. 24
9.2.6. Region 1 Descriptor.................................................................. 24
9.2.7. Runtime Registers .................................................................... 24
9.2.8. Interrupt Control/Status Register .............................................. 24
9.2.9. EEPROM, PCI, User IO............................................................ 25
10. EEPROM Contents ............................................................................. 26

Table of Contents

ADM-XRC-II User Manual
ADM-XRC-II User Manual
Version 1.5