EUROCOM A110SU Service Manual page 60

Schematic Diagrams
Processor 2/7
D
Sheet 3 of 46
Processor 2/7
C
B
25 H_PROCHOT_EC
Buffered reset to CPU
A
14,28,33
B - 4 Processor 2/7
5 4
Haswell Processor 2/7 ( MISC,JTAG,CLK )
15,25 H_PECI
R47 R47
40 H_PROCHOT#
15 H_THRMTRIP#
R69 R69
1.05V_LAN_M
13 H_PM_SYNC
H_CPUPWRGD
15 H_CPUPWRGD
PMSYS_PWRGD_BUF R44 R44
CPU_RST_N R49 R49
15 CPU_RST_N
BUF_CPU_RST# R50 R50
19 PCH_CK_DP_N
19 PCH_CK_DP_P
19 PCH_SSC_N
19 PCH_SSC_P
19 CLK_EXP_N
19 CLK_EXP_P
1.05V_LAN_M VCCIO_OUT
*75_04 *75_04 R37 R37 CPU_RST_N
H_PROCHOT#
Q3 Q3
S3 circuit:- DRAM PWR GOOD logic
C39 C39
G
MTN7002ZHS3 MTN7002ZHS3
47P_50V_NPO_04 47P_50V_NPO_04
R26 R26
100K_04 100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin
13 PM_DRAM_PWRGD
BUF_CPU_RST#
R39 R39 *2K_1%_04 *2K_1%_04
BUF_PLT_RST#
R38 R38
*1K_1%_04 *1K_1%_04
5 4
3
U40B U40B Haswell rPGA EDS Haswell rPGA EDS
SKTOCC# AP32 MISC MISC
SKTOCC SM_RCOMP_0
SM_RCOMP_1
H_CATERR#
AN32
CATERR SM_RCOMP_2
AR27
PECI SM_DRAMRST
FC_AK31
AK31
FC_AK31
56_1%_04 56_1%_04 H_PROCHOT#_R
AM30
PROCHOT PRDY
AM35
THERMTRIP PREQ
TCK
*100_1%_04 *100_1%_04
TMS
TRST
AT28
PM_SYNC TDI
AL34
PWRGOOD TDO
130_1%_04 130_1%_04 VDDPWRGOOD_R
AC10
SM_DRAMPWROK DBR
*10mil_short *10mil_short CPU_RST#
AT26
PLTRSTIN
*0_04 *0_04
BPM_N_0
BPM_N_1
G28
DPLL_REF_CLKN BPM_N_2
H28
DPLL_REF_CLKP BPM_N_3
F27
SSC_DPLL_REF_CLKN BPM_N_4
E27
SSC_DPLL_REF_CLKP BPM_N_5
D26
BCLKN BPM_N_6
E26
BCLKP BPM_N_7
2 OF 9 2 OF 9
PZ94721-3622 PZ94721-3622
SSC CLOCK TERMINATION STUFF
ONLY WHEN SSC CLOCK NOT USED
R24 R24 *0_06 *0_06
1.05V_LAN_M
R92 R92 *10K_04 *10K_04 PCH_SSC_P
R91 R91 *10K_04 *10K_04 PCH_SSC_N
V_VDDQ_DIMM
R29 R29
1.82K_1%_04 1.82K_1%_04
R43 R43 *10mil_04 *10mil_04 PMSYS_PWRGD_BUF
R42 R42
3.32K_1%_04 3.32K_1%_04 R30 R30 R31 R31
*39_04 *39_04 *100K_04 *100K_04
PWRGD_BUF
Q4 Q4
G
23,24,34,38,39 SUSB
*MTN7002ZHS3 *MTN7002ZHS3
11,12,13,15,16,17,18,19,20,21,22,25,27,29,33,34,35,37,38,39,41,42
5,9,10,11,12,13,14,15,17,18,19,21,24,25,26,27,28,30,31,33,34,35,36,40
3
2 1
PU/PD for JTAG signals
AP3 SM_RCOMP_0
AR3 SM_RCOMP_1
SM_RCOMP_2 XDP_TMS R22 R22 *51_04 *51_04
AP2
CPUDRAMRST# XDP_TDI_R R23 R23 *51_04 *51_04
AN3
XDP_PREQ# R48 R48 *51_04 *51_04
XDP_PRDY# XDP_TDO_R R70 R70 51_04 51_04
AR29
AT29 XDP_PREQ# XDP_TCLK R68 R68 51_04 51_04
XDP_TCLK XDP_TRST# R67 R67 51_04 51_04
AM34
XDP_TMS XDP_TDO_R R73 R73 *100_04 *100_04
AN33
XDP_TRST#
AM33
XDP_TDI_R
AM31
AL33 XDP_TDO_R
XDP_DBR_R
AP33
XDP_BPM0 XDP_DBR_R 1K_04 1K_04 R25 R25
AR30
XDP_BPM1
AN31
AN29 XDP_BPM2
AP31 XDP_BPM3
XDP_BPM4
AP30 DDR3 Compensation Signals
XDP_BPM5
AN28
XDP_BPM6
AP29
AP28 XDP_BPM7
SM_RCOMP_0 R56 R56 100_1%_04 100_1%_04
SM_RCOMP_1 R57 R57 75_1%_04 75_1%_04
SM_RCOMP_2 R59 R59 100_1%_04 100_1%_04
Processor Pullups/Pull downs
FC_AK31
H_PROCHOT# R27 R27 62_04 62_04
C36 C36 C37 C37
*22u_6.3V_X5R_08_E *22u_6.3V_X5R_08_E *22u_6.3V_X5R_08_E *22u_6.3V_X5R_08_E H_CPUPWRGD R76 R76 10K_04 10K_04
C46 C46 *0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04
TRACE WIDTH 10MIL, LENGTH <500MILS
S3 circuit:- DRAM_RST# to memory
should be high during S3
V_VDDQ_DIMM
R45 R45 *0_04 *0_04
BSS138 ( VGS 1.5V ) R32 R32
1K_04 1K_04
Q5 Q5
MTN7002ZHS3 MTN7002ZHS3
CPUDRAMRST# S D C_D_RST#
R33 R33 1K_04 1K_04
R58 R58
DDR3_DRAMRST# 9,10
4.99K_1%_04 4.99K_1%_04
DRAMRST_CNTRL 4,12
C40 C40
0.047u_10V_X7R_04 0.047u_10V_X7R_04
! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/
Title Title Title
[03] PROCESSOR 2/7 [03] PROCESSOR 2/7 [03] PROCESSOR 2/7
VDD3
3.3VS
4,6,9,10,39 V_VDDQ_DIMM
Size Size Size Document Number Document Number Document Number
6,17,18,29,35,40,41 1.05V_LAN_M 6-71-A11S0-D02 6-71-A11S0-D02 6-71-A11S0-D02
A3 A3 A3 SCHEMATIC1 SCHEMATIC1 SCHEMATIC1
5,6,40 VCCIO_OUT
Date: Date: Date: Monday, August 19, 2013 Monday, August 19, 2013 Monday, August 19, 2013 Sheet Sheet Sheet
2 1
D
1.05V_LAN_M
3.3VS
C
VCCIO_OUT
B
A
Rev Rev Rev
1.0 1.0 1.0
3 3 3 of of of 46 46 46