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Signal REFRESH# indicates a memory refresh cycle. It is generated as an output
signal by the refresh control. As an input signal, it must be generated by a busmas-
ter (open collector or tri-state driver) every 15 s if the busmaster uses the bus for
more than 10 s. During a refresh, the refresh address is on lines SA0 - SA15.
This signal provides a frequency of 14.31818 MHz that can be used e.g. to generate
the color signal of a CRT controller. It may also be used as a timer cycle. It is asyn-
chronous to the system cycle and has a cycle ratio of 1:1.
This signal is used to reset the control logic on ISA expansion boards. RETDRV is
set by the Reset-Controller on power-up of the computer and after a bus time-out.
The interrupt signals are used to interrupt program currently executed by the pro-
cessor and indicates that an I/O device needs to be attended by the CPU. Their
priority is 9, 10, 11, 12, 14, 15, 3, 4, 5, 6, 7 (in descending order). A CPU interrupt
is initiated either by a flank or a level. The interrupt signal must be held until the
processor has executed the appropriate INTA cycles. Since that can not be detected
on the bus (no INTACK line), an Interrupt-Hold-Flip-Flop must be present for ev-
ery interrupt signal. The flip-flop must be reset by an I/O command, which acknowl-
edges the interrupt.
An expansion board can indicate an error via this signal to the processor (e.g. a par-
ity error), if IOCHK# was enabled prior by writing bit 3 to the port address 61h. In
that case, a NMI can be created, if it is enabled via bit 7 (=0) on the I/O-address 70h.
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