Aaeon PCM-4330 Instructions Manual page 85

The system timer in the SIS-85C471-AT-Controller includes all 82C54 timer func-
tions. It contains three AT-compatible, independently running and programmable
counters for software controlled generation of precise time intervals (counter 0, 1
and 2)
Counter 0 is connected to the interrupt request 0 of the Master-Interrupt-Controller.
It has the highest priority of all maskable interrupts. Counter 0 has to interrupt the
CPU every 50 ms to provide necessary time-updates. It is always active.
Counter 1 works in mode 2, programmed to update the memory refresh logic every
15 s. Counter 1 is always active.
Counter 2 operates in mode 3, programmed as a square-wave generator to control
the speaker. It is controlled by gate 2 via System-Control-Latch-Bit 0 (I/O port
61h). The output of counter 2 is combined by a logical and with bit 1 of the Port-B-
Register to generate output signals for the speaker.
The timer is addressed as a 8-bit periph-
eral at I/O address 40h to 43h.
Counters are programmed by writing the
control word and then the initial counter
state into the memory location of the
counter. Please refer to the SIS-85C471
product documentation (Lit. [3]) for de-
tailed information.
Timer 1, System Timer
040h
(Counter 0)
Timer 1, Refresh Request
041h
(Counter 1)
Timer 1, Speaker Tone
042h
(counter 2)
Timer 1, Control Word
043h
Register