Aaeon PCM-4330 Instructions Manual page 54

The following section describes the meaning and specific attributes of individual
signal. Signals with # symbol are low active.
SD0 - SD15
Data is transferred on these lines between CPU / DMA, memory and I/O. 8-bit
boards must use lines SD0 - SD7 while 16-bit boards use lines SD0 - SD15. A
16-bit processor access to an 8-bit board automatically results in the generation of
two 8-bit accesses. More significant data is shifted by a swap buffer to D0 - D7 with
High-Byte-Access.
LA17 - LA23
LA17- LA23 represent the unlatched address bus. Together with lines SA0 - SA19
of the ISA Bus, they address a memory area of up to 16 MB. Lines must be latched
by a BALE signal. Output signals are generated by the CPU or a busmaster, input
signals must be generated by a busmaster.
SA0 - SA19
These lines are used on the ISA-bus to address memory and I/O devices. They are
stable during Command Phase and need not be latched. They are generated as out-
put signals by the CPU or the DMA controller. Input signals must be generated by
a busmaster. During a refresh cycle — indicated by a REFRESH# signal — lines
SA0 - SA9 carry the dynamic memory's refresh address.
SBHE#
This low active signal indicates data transfer on data lines SD8 - SD15. It may only
be used for control of data bus drivers and write signals on the ISA-bus with 16-bit
boards.
AEN
This low active signal specifies the I/O address space. AEN is the result of a logical
and of signals HOLDA and MASTER# and indicates that a DMA controller or the
refresh logic has taken control of the bus. It must always be used for I/O address
coding for expansion cards.
SYSCLK
This signal is a synchronous signal to the system cycle on the AT-bus with a fre-
quency of 8.25 MHz and a cycle proportion of 1:1(50%).
BALE
This signal is the result of a logical or of signals ALE and HOLDA. Addresses
LA17- LA23 must be latched with this signal. It is not generated for the second
cycle of a 16-bit access to an 8-bit board and may thus not be evaluated as the
beginning of a cycle. Due to the or operation, signal BALE is high during DMA or
refresh cycles.