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The low active signal MEMCS16# indicates that the data transfer is a 16-bit access
to memory. It must be generated by i6-bit memory units from addresses LAI7 -
LA23. These memory accesses require one wait state with an access time of 220
ns. If this is not sufficient, additional wait states must be inserted by asserting
CHRDY. The signal must be asserted by an open collector or tri-state driver.
This active low signal indicates that the current data transfer is a 16-bit I/O transfer.
It must be generated by 16-bit I/O units from addresses SA1 - SA15. These trans-
fers require one wait state with an access time of 220 ns. If this is not sufficient,
additional wait states must be inserted by asserting CHRDY. The signal must be
asserted by an open collector or tri-state driver.
An expansion component can request an I/O
memory or memory
I/O trans-
fer or an ISA busmaster can request use of the bus by asserting the asynchronous
DMA request lines. DRQ0 has the highest priority. The request is asserted by a high
signal that must be maintained until the DMA controller responds with a DACK#
signal. DRQ0 - DRQ3 can only be used to request byte (8-bit) transfers while DRQ5
- DRQ7 can only be used to request word (16-bit) transfers at even addresses
(SBHE=0, A0=0). A DMA request can also be used to allow an expansion card to
become a busmaster if the DMA channel is programmed in Cascade Mode and if
the expansion card generates a MASTER# signal after receiving a DACK# signal.
The DACK# signals indicate that a DMA request is acknowledged by the DMA
controller and that the DMA transfer can occur. These signals are used by the expan-
sion cards as I/O select signals for the selected data register. An expansion card that
wants to become bus master will generate a MASTER# signal in response to receiv-
ing a DACK# signal.
This signal is bi-directional depending on the mode in which the DMA controller
was programmed. In output mode, the TC signal indicates that a DMA transmis-
sion is finished. In input mode, a DMA slave may cancel a DMA transmission with
this signal.
This signal, together with an DRQn / DACKn# pair, lets an expansion card become
busmaster. The DMA channel must be programmed in Cascade Mode. After receiv-
ing the DACK# signal, the expansion card sets the MASTER# signal to low. One
system cycle later (I25 ns) it may assume control of the address and data bus, an-
other cycle later of the read and write lines. If a busmaster wants to retain control of
the bus longer than 50 s, it must refresh the memory every 15 s to avoid loss of
data. Signal MASTER# must be asserted by an open collector or tri-state driver.
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