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The tone signal for the speaker is generated by Timer 2 (in the SIS-85C471-AT-
Controller). The timer is programmed as a square-wave generator. The generator is
controlled by the System-Control-Registers in Port B. An additional bit of the Sys-
tem-Control-Registers is combined with output of Timer 2 by a logical and.
Theresulting signal controls the internal or external speaker (using the system inter-
face; c.f. Figure 23 on page 54).
A system reset may be initiated by the power supply, shutdown, keyboard reset or
via I/O port 92h (Bit 0) and the SIS-85C471-AT-Controller.
The CPU line mask-A20 can be controlled as in AT-systems through the key-board
®
controller. Additionally, the PS/2
-compatible port 92h (Bit 1) is available.
The status and control port B (061h) consists of the integrated System-Control-
Register and the System-Status-Buffer. Parity checking may be enabled/disabled
via the System-Control-Register. The System-Status-Buffer informs on queued
memory parity errors.
The Western Digital WD90C24 video controller can address various monochrome
or color flat panel displays directly, as well as regular SVGA monitors. A 2-row 10-
pin connector for SVGA displays and a 2-row 40-pin universal LCD-onnector
arelocated on the board.
The FDC37C92x-Ultra-I/O-Controller from SMC with a licensed 765B-compatible
TM
SuperCell
is used for floppy disk control. Data is exchanged over DMA channel2,
1/2
1/4
interrupts are initiated via IRQ6. Up to two floppy disk drives (3
or 5
) are sup-
ported.
The FDC37C92x peripheral unit also includes an interface for IDE-/AT-bus hard
disks.
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