Aaeon PCM-4330 Instructions Manual page 55

Signal SMEMR# indicates a read cycle, SMEMW# a write cycle within the first
MB of the ISA memory area (000000H-0FFFFFH). These signals are generated by
the CPU or DMA controllers, signal SMEM R# is also generated by the refresh
logic during refresh cycles with lines SA0 - SA9 indicating the refresh address.
SA10- SA16 are in state high-impedance! SA17 - SA19 and LA17 - LA23 are kept
on low by the page register. Signal REFFRESH# indicates that this is a refresh cycle
in contrast to a normal read.
Signal MEMR# indicates a read, signal MEMW# a write cycle within the 16 MB
ISA address space. Output signals are generated by the CPU or by DMA control-
lers. For signal MEMW#, the refresh cycle operates analog to the SMEMR# signal.
Input signals must be driven by a busmaster.
Signal IOR# indicates a read, signal IOW# a write cycle on an I/O device if signal
AEN is active at the same time. Output signals are generated by the CPU or the
DMA controllers. Input signals must be forced by a busmaster. Since the Slot-CPU
does not support full address decoding of I/O addresses, only a limited address
space of 000h - 3FFh is available for expansion cards. Therefore, lines SA10 - SA15
need not be coded for I/O devices.
This asynchronous signal is used to prolong the standard access times preset on
the Slot-CPU for memory and port access. Slow boards generate this signal from
the board address and the read/write signal. The CPU, DMA controller or refresh
logic insert waitstates while this signal is set to low (NOT-READY). This signal
should only be used if an access time of 500 ns for 8-bit or 220 ns for 16-bit ISA
boards is insufficient. It must not be held by a ISA slave board for longer than 2.1
s to avoid loss of data due to an overdue refresh cycle.
The synchronous ready signal WS0# notifies the buslogic that the peripheral
inserted into the expansion slot does not require wait states. In order to satisfy the
setup and hold times of the peripheral, this signal must be logically combined with
the processor synchronous signals: IOR#, IOW#, SMEMR#, SMEMW#, MEMR#,
MEMW# and SYSCLK. To allow 16-bit memory access to a peripheral to proceed
without waitstates (access time 100 ns), WS0# must be generated by combining
the address and the read/write signal. If an 8-bit bus cycle with a minimum of 2
wait states is to occur, WS0# must be asserted (combined with the address coding)
one clock cycle after the READ or WRITE signal is asserted. The signal must be
asserted by an open collector or tri-state driver.