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System BIOS
3.3.3.1
Memory Reservation for Memory-mapped Functions
A region of size 512 MB of memory below 4 GB is always reserved for mapping chipset,
processor and BIOS (flash) spaces as memory-mapped I/O regions. This region will appear as
a loss of memory to the operating system. In addition to this loss, the BIOS creates another
reserved region for memory-mapped PCI Express* functions, including a standard 1.0 GB of
standard PC Express configuration space. This memory or portions thereof may be reclaimed
by the operating system if PAE is turned on in the OS.
3.3.3.2
High-Memory Reclaim
When 4 GB or more of physical memory is installed, the reserved memory is lost. However, the
®
Intel
5000 Series Chipset provides a feature called high-memory reclaim that allows the BIOS
and the operating system to remap the lost physical memory into system memory above 4 GB.
The system memory is the memory that can be seen by the processor.
The BIOS will always enable high-memory reclaim if it discovers installed physical memory
equal to or greater than 4 GB. For the operating system, the reclaimed memory is recoverable
only when it supports and enables the PAE feature in the processor. Most operating systems
support this feature. See the relevant operating system manuals for operating system support in
your environment.
3.3.4
Mixed Speed Memory Modules
The BIOS supports memory modules of mixed speed through a combination of user-selected
input frequency and the capability of each memory module (FBDIMM). This section describes
the expected outcome on installation of FBDIMMs of different frequencies in the system, for a
given user-selected frequency.
3.3.4.1
FBDIMM Characteristics
To program a FBDIMM to function correctly for a given frequency, the BIOS queries each
FBDIMM's Serial-presence Data (SPD) store. The SPD contains the frequency characteristics
of the FBDIMM, which are measured in terms of the following parameters:
CAS latency (CL)
Common clock frequency
Additive latency (AL)
Buffer read delay (BRD)
The CAS latency and the additive latency are configurable parameters that are detected by the
BIOS by reading the SPD data of the FBDIMMs. The BRD is the average inherent delay that is
caused by the finite time that the AMB consumes in buffering the data read from the DRAMs
before forwarding it on the northbound or southbound path.
32
Intel® 5000 Series Chipsets Server Board Family Datasheet
Intel order number D38960-004
Revision 1.1
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