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Intel® 5000 Series Chipsets Server Board Family Datasheet
2.4
I/O Sub-system
The I/O sub-system consists of several components:
PCI sub-system
Serial ATA (SATA) support
Serial-attached SCSI (SAS)
RAID support
Parallel ATA (PATA) support
Video controller
Network interface controller (NIC)
USB 2.0 support
Super I/O support
This section describes the function of each I/O interface and how they operate.
2.4.1
PCI Sub-system
2.4.2
Scan Order
The BIOS assigns PCI bus numbers in a depth-first hierarchy, in accordance with the PCI Local
Bus Specification, Revision 2.2. The bus number is incremented when BIOS locates a bridge
device that is not part of the chipset. Scanning continues on the secondary side of the bridge
until all subordinate buses are assigned numbers. PCI bus number assignments may vary from
boot to boot with varying presence of PCI devices with PCI-PCI bridges. If a device with a
bridge with a single bus behind it is inserted into a PCI bus, all subsequent PCI bus numbers
below the current bus are increased by one.
The bus assignments occur once, early in the BIOS boot process, and never change during the
pre-boot phase.
2.4.3
Resource Assignment
The BIOS resource manager assigns the PIC-mode interrupt for the devices that are accessed
by the legacy code. The BIOS will ensure the PCI BAR registers and the command register for
all devices are correctly set up to match the behavior of the legacy BIOS after booting to a
legacy operating system. Any legacy code cannot make any assumption about the scan order of
devices or the order in which resources are allocated to them.
In legacy mode, the BIOS supports the INT 1Ah PCI BIOS interface calls.
2.4.4
Automatic IRQ Assignment
The BIOS automatically assigns IRQs to devices in the system for legacy compatibility. No
method is provided to manually configure the IRQs for devices.
Revision 1.1
Intel order number D38960-004
Functional Architecture
17
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