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Intel® 5000 Series Chipsets Server Board Family Datasheet
2.1.1.3.5
PCI Express* Retrain
If the hardware is unable to perform a successful recovery, then the link automatically reverts to
the polling state and initiates a full retraining sequence. This is a drastic event with an implicit
reset to the downstream device and all subordinate devices, and is logged by the Intel
MCH as a "Link Down" error. If escalation of this event is enabled, software is notified of the link
DL_DOWN condition. If software is involved, then data is probably lost, and processes need to
be restarted. This is preferred over the taking down the system or going offline for an extended
time.
2.1.1.4
Enterprise South Bridge Interface (ESI)
A PCI interface is provided for a connection to the memory controller hub (Intel
Maximum realized bandwidth on this interface is 2 GB/s in each direction simultaneously, for an
aggregate of 4 GB/s. This PCI Express* interface is compliant with the PCI Express Base
Specification Revision 1.0a, and supports x4 and x8 bandwidths.
®
2.1.2
Intel
®
The Intel
631xESB / 632xESB I/O Controller Hub is a multi-function device that provides an
upstream hub interface for access to several embedded I/O functions and features, including:
Compliant with the PCI Express Base Specification, Revision 1.0a, with support for four
PCI Express* root ports (module-based hot-plug support) and two 1x4 downstream ports
(connector-based hot-swap support)
Compliant with the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b
Compliant with the PCI Local Bus Specification, Revision 2.3 with support for 33 MHz
PCI operations
Compliant with the PCI Standard Hot-Plug Controller and Subsystem Specification,
Revision 1.0
ACPI 2.0 power management logic support
Enhanced DMA controller, interrupt controller, and timer functions
Integrated IDE controller with support for Ultra ATA100 / 66 / 33
Integrated SATA controller
Baseboard management controller (BMC)
USB host interface with support for eight USB 2.0 ports; via four UHCI host controllers;
and one EHCI high-speed host controller
Compliant with the System Management Bus (SMBus) Specification, Version 2.0 with
additional support for I
Support for the Audio Codec '97, Revision 2.3 Specification
Low pin count (LPC) interface
Each function within the Intel
configuration registers. Once configured, each appears to the system as a distinct hardware
controller that shares the same PCI bus interface.
Revision 1.1
631xESB / 632xESB I/O Controller Hub (ESB2)
2
C devices
®
631xESB / 632xESB I/O Controller Hub has its own set of
Intel order number D38960-004
Functional Architecture
®
5000
®
5000 MCH).
7
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