Memory Error Handling - Intel 5000 Series Datasheet

Hide thumbs Also See for 5000 Series:
Table of Contents

Advertisement

System BIOS
3.3.10

Memory Error Handling

This section describes the BIOS and chipset policies used for handling and reporting errors
occurring in the memory sub-system.
3.3.10.1
Memory Error Classification
The BIOS classifies memory errors into the following categories:
Correctable ECC errors: errors that occur in memory cells and result in corruption of
memory, but are internally corrected by the ECC engine in the chipset.
Uncorrectable ECC errors: errors that occur in memory cells and result in data
corruption. The chipset's ECC engine detects these errors, but cannot correct them.
These errors create a loss of data fidelity and are severe errors.
Unrecoverable and Fatal Errors: errors that are outside of the scope of the standard
ECC engine. These errors are thermal errors, FBD channel errors and data path errors.
These errors bring about catastrophic failure of the system.
There are two specific stages in which memory errors can occur:
Early POST, during memory discovery
Late POST, or at runtime, when the operating system is running
During POST, the BIOS will capture and report memory BIST errors.
Memory RAS configuration errors
At runtime, the BIOS will capture and report correctable, uncorrectable, and fatal errors
occurring in the memory sub-system.
Loss of memory RAS functionality
3.3.10.1.1
Faulty FBDIMMs
The BIOS provides detection of a faulty or failing FBDIMM. An FBDIMM is considered faulty if it
fails the memory BIST. The BIOS enables the in-built memory BIST engine in the Intel
Series Chipsets during memory initialization in POST. The memory BIST cycle isolates failed,
failing, or faulty FBDIMMs and the BIOS then marks those FBDIMMs as failed and takes these
FBDIMMs off-line.
FBDIMMs can fail during normal operation. The BIOS marks these FBDIMMs as temporarily
disabled, and performs other housekeeping tasks as relevant. The memory BIST function is
performed on every FBDIMM during each boot of the system, unless waking from S3.
40
Intel® 5000 Series Chipsets Server Board Family Datasheet
Intel order number D38960-004
®
5000
Revision 1.1

Advertisement

Table of Contents
loading

Table of Contents