Critical Interrupt Sensor; Dimm Status Sensors - Intel 5000 Series Datasheet

Intel® 5000 Series Chipsets Server Board Family Datasheet
4.17.3

Critical Interrupt Sensor

The BMC implements a Critical Interrupt (13h) sensor for reporting the following conditions /
events:
Bus Uncorrectable Error: Only sensed after an SMI timeout (post-mortem)
Front Panel NMI / diagnostic interrupt: Monitored during normal system operation
4.17.4

DIMM Status Sensors

There is one DIMM status sensor per DIMM slot. These sensors are IPMI sensor type Slot /
Connector (21h) and event / reading type Sensor Specific (6Fh). The supported offsets are:
00h Fault Status Asserted
02h Device Installed
08h Device Disabled
09h Slot Holds Spare Device
The BIOS can set or clear individual offsets for the DIMM sensors using the Set DIMM State
command and Get DIMM State commands.
If the BMC is so configured, the BMC stores the DIMM fault and disabled status will be stored
persistently in non-volatile storage. They are re-established at BMC startup.
The state is not stored persistently.
4.17.4.1 Fault Status
The BIOS detects the DIMM fault status and sets the DIMM sensor state when the BIOS detects
an uncorrectable ECC error
4.17.4.2 Device Installed
The BIOS performs DIMM presence detection and sets the DIMM sensor state appropriately at
each system boot.
4.17.4.3 Device Disabled
The BIOS can determine if a FBDIMM should be disabled and sets the DIMM sensor state
4.17.4.4 Slot Holds Spare Device
The DIMM sparing indication is informational and used by the memory redundancy features to
determine the redundancy state.
Revision 1.1
Intel order number D38960-004
System Management
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