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Intel 5000 Series Datasheet

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Intel
5000 Series Chipsets
Server Board Family
Datasheet
Intel order number D38960-004
Revision 1.1
June 01, 2006
Enterprise Platforms and Services Division

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Summary of Contents for Intel 5000 Series

  • Page 1 ® Intel 5000 Series Chipsets Server Board Family Datasheet Intel order number D38960-004 Revision 1.1 June 01, 2006 Enterprise Platforms and Services Division...
  • Page 2 Revision History Intel® 5000 Series Chipsets Server Board Family Datasheet Revision History Date Revision Modifications Number 31 May 06 Initial Document Release. Revision 1.1 Intel order number D38960-004...
  • Page 3 Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 4: Table Of Contents

    Table of Contents Intel® 5000 Series Chipsets Server Board Family Datasheet Table of Contents 1. Introduction...........................1 Server Product References ..................1 Chapter Outline ......................1 2. Functional Architecture .......................2 ® Intel 5000 MCH Components .................4 ® 2.1.1 Memory Controller Hub (Intel 5000 MCH) ..............4 ®...
  • Page 5 Intel® 5000 Series Chipsets Server Board Family Datasheet Table of Contents 2.4.16 Native USB Support ....................21 2.4.17 Legacy USB Support....................21 2.4.18 Super I/O........................21 2.4.19 BIOS Flash......................22 Clock Generation and Distribution .................23 3. System BIOS ........................24 BIOS Identification String ..................24 Processors ......................25 3.2.1...
  • Page 6 Table of Contents Intel® 5000 Series Chipsets Server Board Family Datasheet 3.3.10 Memory Error Handling ..................40 Platform Control .....................53 3.4.1 FBDIMM Open Loop Throughput Throttling ............54 3.4.2 Fan Speed Control ....................55 Flash ROM ......................57 BIOS User Interface ....................57 3.6.1 Logo / Diagnostic Screen ..................57 BIOS Setup Utility ....................58...
  • Page 7 Intel® 5000 Series Chipsets Server Board Family Datasheet Table of Contents 3.17 Non-Maskable Interrupt Handling ................94 3.18 BIOS Server Management ..................94 3.19 IPMI........................94 3.20 Console Redirection....................95 3.20.1 Serial Configuration Settings..................95 3.20.2 Keystroke Mappings....................95 3.20.3 Limitations ......................96 3.20.4 Interface to Server Management................96 3.21...
  • Page 8 Table of Contents Intel® 5000 Series Chipsets Server Board Family Datasheet 4.8.3 Timestamp Clock ....................110 Sensor Data Record (SDR) Repository..............111 4.9.1 Initialization Agent ....................111 4.10 Field Replaceable Unit (FRU) Inventory Device...........111 4.11 Diagnostics and Beep Code Generation..............112 4.12 NMI........................112 4.12.1 Signal Generation ....................113...
  • Page 9 Intel® 5000 Series Chipsets Server Board Family Datasheet Table of Contents 4.17.6 System Memory Monitoring and System Boot .............127 4.18 PCI Express* Support ..................127 4.18.1 PCI Express Link Sensors ...................127 4.18.2 BMC Self-test .......................127 4.19 Field Replaceable Unit (FRU) / Fault LED Control..........128 4.20...
  • Page 10 Table of Contents Intel® 5000 Series Chipsets Server Board Family Datasheet 4.29.4 Address Resolution Protocol Support ..............141 4.29.5 Internet Control Message Protocol Support ............141 4.29.6 Serial-over-LAN (SOL) 2.0 ...................141 5. Error Reporting and Handling ..................142 Fault Resilient Booting (FRB)................142 5.1.1 BSP POST Failures (FRB-2)................142...
  • Page 11 Intel® 5000 Series Chipsets Server Board Family Datasheet List of Figures List of Figures ® Figure 1. Intel 5000 MCH Functional Architechture..............3 Figure 2. CEK Processor Mounting.....................13 Figure 3. FBD Topology ......................15 Figure 4. Identifying Banks of Memory..................16 Figure 5. General BIOS Screen Display Layout ................59 Figure 6.
  • Page 12 List of Tables Intel® 5000 Series Chipsets Server Board Family Datasheet List of Tables Table 1. DIMM Module Capacities ....................16 Table 2. NIC2 Status LED ......................20 Table 3. Supported Processor Configurations ................25 Table 4. Mixed Processor Configurations ...................27 Table 5. Memory Errors Captured by Error Manager ..............45 Table 6.
  • Page 13 Intel® 5000 Series Chipsets Server Board Family Datasheet List of Tables Table 34. BMC Reset Sources and Actions ................103 Table 35. Power LED Indicator States ..................105 Table 36. System Status LED Indicator States .................106 Table 37. Chassis ID LED Indicator States ................107 Table 38.
  • Page 14 List of Tables Intel® 5000 Series Chipsets Server Board Family Datasheet This page intentionally left blank Revision 1.1 Intel order number D38960-004...

  • Page 15: Introduction

    This document applies to both specific Intel server boards and to specific Intel workstation boards. Unless otherwise noted, all references to “Intel boards” or “board” apply to both server boards and workstation boards that use this chipset. Chapter Outline This document is divided into the following chapters...

  • Page 16: Functional Architecture

    Functional Architecture Intel® 5000 Series Chipsets Server Board Family Datasheet Functional Architecture This chapter provides a detailed description of the functionality associated with the ® architectural blocks that comprise the Intel 5000 MCH. A diagram of the chipset functional architecture is on the following page.

  • Page 17: Figure 1. Intel 5000 Mch Functional Architechture

    Intel® 5000 Series Chipsets Server Board Family Datasheet Functional Architecture ® Figure 1. Intel 5000 MCH Functional Architechture Revision 1.1 Intel order number D38960-004...

  • Page 18: Intel ® 5000 Mch Components

    This allows a total of 25.6 GB/s and 64.6 GB/s peak theoretical bandwidth for all four Channels combined. One PCI Express* x8 port with an aggregate bandwidth of 4 GB/s interface to the Intel® 631xESB / 632xESB I/O Controller Hub.
  • Page 19 Intel® 5000 Series Chipsets Server Board Family Datasheet Functional Architecture ® 2.1.1.2 Intel 5000 MCH Memory Sub-System Overview ® The Intel 5000 MCH provides an integrated memory controller for direct connection to four channels of registered fully-buffered DIMM (FBD) DDR2 533/667 MHz memory (stacked or unstacked).
  • Page 20 Functional Architecture Intel® 5000 Series Chipsets Server Board Family Datasheet 2.1.1.3.1 PCI Express* Training To establish a connection between PCI Express* endpoints, the endpoints participate in a sequence of steps called training. This sequence establishes the operational width of the link and adjusts skews of the various lanes within a link so that the data sample points can correctly take a data sample from the link.

  • Page 21: Intel ® 631Xesb / 632Xesb I/O Controller Hub (Esb2)

    This is a drastic event with an implicit ® reset to the downstream device and all subordinate devices, and is logged by the Intel 5000 MCH as a "Link Down" error. If escalation of this event is enabled, software is notified of the link DL_DOWN condition.
  • Page 22 631xESB / 632xESB I/O Controller Hub PCI interface supports a 33-MHz, Revision 2.3-compliant implementation. All PCI signals are 5-V tolerant, except for PME#. An integrated ® PCI arbiter supports up to six external PCI bus masters in addition to the internal Intel ® ®...
  • Page 23 Technology that enables data striping (RAID Level 0) for higher-performance or data mirroring (RAID Level 1) for fault-tolerance between the two SATA drives, alleviating disk bottlenecks by ® taking advantage of the dual, independent SATA controllers integrated in the Intel 631xESB / 632xESB I/O Controller Hub.
  • Page 24 2.1.2.9 Advanced Programmable Interrupt Controller (APIC) ® In addition to the standard ISA-compatible PIC described in the previous section, the Intel 631xESB / 632xESB I/O Controller Hub incorporates the Advanced Programmable Interrupt Controller (APIC). 2.1.2.10 Universal Serial Bus (USB) Controller ®...

  • Page 25: Processor Sub-System

    Intel® 5000 Series Chipsets Server Board Family Datasheet Functional Architecture 2.1.2.11 Real-time Clock (RTC) ® The Intel 631xESB / 632xESB I/O Controller Hub contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of battery-backed RAM. The real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered down.

  • Page 26: Processor Support

    Intel Common Enabling Kit (CEK) processor mounting and thermal solution. The server board ships from Intel’s factory with a CEK spring snapped onto the underside of the board beneath each processor socket. The CEK spring is removable to allow the use of non-Intel heat sink retention solutions.

  • Page 27: Memory Sub-System

    Intel® 5000 Series Chipsets Server Board Family Datasheet Functional Architecture Heatsink assembly Thermal Interface Material (TIM) TP02091 Server Board CEK Spring Chassis AF000196 Figure 2. CEK Processor Mounting Memory Sub-system ® ® The Intel boards that use the Intel 5000 MCH support several fully-buffered (FBD) memory modes of operation.

  • Page 28: Fully-Buffered Dimm (Fbdimm)

    Functional Architecture Intel® 5000 Series Chipsets Server Board Family Datasheet In non-mirrored operation, the two DDR2 channels within a branch operate in lock-step and the branches operate independently. When memory mirroring is configured, the channels operate in lock-step under normal conditions, but independently under failure and recovery conditions.

  • Page 29: Supported Memory

    512 MB, using a single DIMM in the DIMM A1 socket. Note: All Intel memory qualification is done by testing with complete memory banks of identical memory modules in all DIMM sockets. Memory qualification does not include testing of single- channel memory mode, mixed DIMM type and/or vendors.

  • Page 30: Figure 4. Identifying Banks Of Memory

    Functional Architecture Intel® 5000 Series Chipsets Server Board Family Datasheet Table 1. DIMM Module Capacities SDRAM Parts / SDRAM Technology Used 512Mb X8, single row 512MB X8, double row X4, single row 512MB X4, Stacked, double row DIMMs on channel A are paired with DIMMs on channel B to configure 4-way interleaving. Each DIMM pair is referred to as a bank.

  • Page 31: I/O Sub-System

    Intel® 5000 Series Chipsets Server Board Family Datasheet Functional Architecture I/O Sub-system The I/O sub-system consists of several components: PCI sub-system Serial ATA (SATA) support Serial-attached SCSI (SAS) RAID support Parallel ATA (PATA) support Video controller Network interface controller (NIC) USB 2.0 support...

  • Page 32: Legacy Option Rom Support

    Functional Architecture Intel® 5000 Series Chipsets Server Board Family Datasheet 2.4.5 Legacy Option ROM Support The legacy support code in the BIOS will dispatch the legacy option ROMs in the available memory space in the address range 0C0000h-0DFFFFh and will follow all the legacy rules with respect to the option ROM space.

  • Page 33: Serial Ata (Sata) Support

    Intel® 5000 Series Chipsets Server Board Family Datasheet Functional Architecture 2.4.9.1 Ultra ATA/100 ® The IDE interface of the Intel 631xESB / 632xESB I/O Controller Hub ICH DMA protocol redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 100 MB/s.

  • Page 34: Sata Raid Functionality

    Functional Architecture Intel® 5000 Series Chipsets Server Board Family Datasheet 2.4.11 SATA RAID Functionality See the server or workstation Technical Product Specification that applies to your product for information. 2.4.12 Serial Attached SCSI See the server or workstation Technical Product Specification that applies to your product for information.

  • Page 35: Native Usb Support

    Intel® 5000 Series Chipsets Server Board Family Datasheet Functional Architecture 2.4.16 Native USB Support During the power on self-test (POST), the BIOS initializes and configures the USB subsystem in accordance with chapter 14 of the Extensible Firmware Interface Reference Specification, Version 1.1.

  • Page 36: Bios Flash

    2 MB is programmable. The flash ROM contains system initialization routines, a setup utility, and runtime support routines. The layout is subject to change, as determined by Intel. The flash ROM contains the necessary drivers for onboard peripherals such as SCSI, Ethernet, and video controllers.

  • Page 37: Clock Generation And Distribution

    5000 MCH, which includes x4 PCI Express slot. For SATA this is the ® Intel 631xESB / 632xESB I/O Controller Hub ICH6. ® 66 MHz at 3.3V logic levels: for 5000 North Bridge and the Intel 631xESB / 632xESB I/O Controller Hub ICH6. ® 48 MHz at 3.3V logic levels: for Intel 631xESB / 632xESB I/O Controller Hub ICH6 and SIO.

  • Page 38: System Bios

    Intel Platform Innovation Framework for EFI architecture specifications specified in the Extensible Firmware Interface Reference Specification, Version 1.1. The Intel Platform Innovation Framework for EFI is referred to as “Framework” in this document.

  • Page 39: Processors

    However, the BIOS power-on self-test (POST) code requires only one processor for ® execution. This requires the BIOS to elect a system BSP using registers in the Intel 5000 MCH. The BIOS cannot guarantee which processor will be the system BSP, only that a system BSP will be selected.

  • Page 40: Mixed Processor Steppings

    If the system BIOS detects a processor for which a microcode update is not available, the BIOS reports an error to the BMC. See Table 4. IA-32 processors can correct specific errata by loading an Intel-supplied data block, known as a microcode update. The BIOS stores the update in non-volatile memory and loads it into each processor during POST.

  • Page 41: Table 4. Mixed Processor Configurations

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Halt: If the system can boot it will go directly to the error manager, regardless of the “Post Error Pause” setup option. Pause: If “Post Error Pause” setup option is enabled, system will go directly to the error manager.

  • Page 42: Hyper-Threading Technology

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet Error Severity System Action Processor system bus Halt The BIOS detects the error condition and responds as follows: speeds not identical Logs the error into the system event log (SEL)

  • Page 43: Execute Disable Bit Feature

    3.2.13 Execute Disable Bit Feature ® The Execute Disable Bit feature (XD bit) is an enhancement to the IA-32 Intel architecture. An IA-32 processor that supports the Execute Disable Bit feature can prevent data pages from being used by malicious software to execute code. An IA-32 processor with the XD bit feature can provide memory protection in either of the following modes: Legacy protected mode if the Physical Address Extension (PAE) is enabled.

  • Page 44: Intel ® Virtualization Technology

    The BIOS supports various memory module sizes and configurations. These combinations of sizes and configurations are valid only for FBDIMMs approved by Intel. The BIOS reads the Serial Presence Detect (SPD) SEEPROMs on each installed memory module to determine the size and timing characteristics of the installed memory modules (FBDIMMs).

  • Page 45: Post Error Codes

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS 3.3.2 POST Error Codes The range {0xE0, 0xEF} of POST codes is used for memory errors in early POST. In late POST, this range is used for reporting other system errors.

  • Page 46: Mixed Speed Memory Modules

    ® Intel 5000 Series Chipset provides a feature called high-memory reclaim that allows the BIOS and the operating system to remap the lost physical memory into system memory above 4 GB. The system memory is the memory that can be seen by the processor.

  • Page 47: Memory Test

    3.3.4.2 Host Frequency and Gear Ratio ® The host frequency is the speed of the memory interface of the Intel 5000 Series Chipset. This frequency determines the speed at which the chipset completes a memory transaction. The gear ratio determines the relative speed between the processor interface and the memory interface.

  • Page 48: Memory Map And Population Rules

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet Demand scrubbing is not possible when memory mirroring is enabled. Therefore, the BIOS will disable it automatically if the memory is configured for mirroring. Note: Memory sparing and mirroring features are currently disabled and will be made available after production launch.
  • Page 49 The existing FBDIMM population The FBDIMM characteristics The optimization techniques used by the Intel® 5000 MCH to maximize FBD bandwidth. In dual-channel mode, the adjacent channels of a branch work in lock-step to provide increase in FBD bandwidth. Channel A and Channel B are lock-stepped when Branch 0 is configured to support dual-channel mode, Channel C and Channel D are lock-stepped when Branch 1 is configured for lock-step.

  • Page 50: Memory Modes Of Operation

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet technology, and size. Therefore, DIMM_A1 and DIMM_B1 must be identical for Branch 1 to work in dual-channel mode. If the FBDIMMs on adjacent channels of a branch are not identical, the FBDIMM on the higher channel is disabled.
  • Page 51 ® All versions of the Intel 5000 Series Chipset provide memory sparing capabilities. Sparing is a RAS feature that involves configuring of a FBDIMM on the server board to be placed in reserve so it can be use to replace an FBDIMM that fails.
  • Page 52 System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet For example: Correct configurations for Branch 0 are DIMM A1, DIMM A2. An incorrect configuration for Branch 0 is DIMM A1. Because there is only one FBDIMM, none is available to act as a spare.
  • Page 53 Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS 3.3.9.4.1 Minimum FBDIMM Population for Mirroring Memory mirroring requires the following minimum requirements: Branch configuration: Mirroring requires both branches to be active. Interleave configuration: Mirroring requires that interleaving at the channel level be enabled on both branches such that the FBDIMMs on the adjacent channels work in lock-step.

  • Page 54: Memory Error Handling

    The BIOS provides detection of a faulty or failing FBDIMM. An FBDIMM is considered faulty if it ® fails the memory BIST. The BIOS enables the in-built memory BIST engine in the Intel 5000 Series Chipsets during memory initialization in POST. The memory BIST cycle isolates failed, failing, or faulty FBDIMMs and the BIOS then marks those FBDIMMs as failed and takes these FBDIMMs off-line.
  • Page 55 Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS 3.3.10.1.2 Faulty Links FBDIMM technology is a serial technology. Therefore, errors or failures can occur on the serial path between FBDIMMs. These errors are different from ECC errors, and do not necessarily occur as a result of faulty FBDIMMs.
  • Page 56 System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet 4. The BMC lights the DIMM fault LED for the faulty FBDIMM. 3.3.10.1.4 Multi-bit Correctable Error Counter Threshold Due to the internal design of the chipset, the same threshold value for correctable errors also applies to the multi-bit correctable errors.
  • Page 57 Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS 3.3.10.1.6 Error Period The error period, or decay rate, defines the rate at which the leaky bucket counter values are decremented. The decay period is the time period for the leaky bucket count to decay to 0.
  • Page 58 Index into SMBIOS Type16 entry for the system’s Memory Array Device. For Intel server boards ® and systems that use the Intel 5000 Series Chipsets this shall always be 0 to indicate that a single on-board memory controller is present. Bits [5:0] Index into SMBIOS Type17 record for the failed FBDIMM.

  • Page 59: Table 5. Memory Errors Captured By Error Manager

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS 3.3.10.2.2 Memory BIST Error Reporting The error manager screen in the BIOS captures memory BIST failures that occurred during the current POST. Table 5. Memory Errors Captured by Error Manager...

  • Page 60: Table 7. System Status Indicator Leds

    3.3.10.2.4 System Status Indicator LEDs Intel server boards have a system status indicator LED on the front panel. This indicator LED is used to indicating many different system errors. The table below shows the policies that are specific to memory errors.

  • Page 61: Table 8. Nmi Generation

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS The LEDs are controlled by the BMC, but the BIOS informs the BMC of the memory errors that are described in the table. The methods used to inform the BMC of the error(s) are described section 3.3.10.2.1.

  • Page 62: Table 9. Mirroring Mode Errors

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet 3.3.10.3 Mirroring Mode Errors When mirroring mode is enabled, the BIOS will report errors in accordance with the following table: Table 9. Mirroring Mode Errors Event Actions Mirroring mode selected by the user, but the BIOS failed Error message in the error manager at end of POST.

  • Page 63: Table 10. Post Memory Error Handling

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Table 10. POST Memory Error Handling Scenario POST Message LED State IPMI MEM States System Operation Updated POST Memory BIST Uncorrectable error UE POST code DIMM LED: Lit for the...

  • Page 64: Table 11. Runtime Memory Error Handling, No Redundancy

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet Table 11. Runtime Memory Error Handling, No Redundancy Scenario POST Message LED State IPMI MEM States System Operation Updated Runtime: None, because the CE SEL message with DIMM DIMM fault LED: Not lit.

  • Page 65: Table 12. Runtime Error Handling, With Redundancy

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Table 12. Runtime Error Handling, with Redundancy Scenario POST Message LED State IPMI MEM States System Operation Updated Runtime: None, because the CE SEL message DIMM fault LED: The system continues to operate...
  • Page 66 System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet Scenario POST Message LED State IPMI MEM States System Operation Updated Runtime: None, because the UE SEL message DIMM fault LED: Fail status = Y The system will NMI. BIOS does not retain...

  • Page 67: Platform Control

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Platform Control This server platform has embedded platform control which is capable of automatically adjusting system performance and acoustic levels. Platform control optimizes system performance and acoustics levels through: Performance management...

  • Page 68: Fbdimm Open Loop Throughput Throttling

    3.4.1 FBDIMM Open Loop Throughput Throttling Memory throttling is a feature of the Intel 5000 sequence chipsets to prevent FBDIMM memory from overheating. If the performance of the installed FB-DIMMs approaches their supported thermal limit for a given platform, system BIOS will initiate memory throttling which manages memory performance by limiting bandwidth to the DIMMs, therefore capping the power consumption and preventing the DIMMs from overheating.

  • Page 69: Fan Speed Control

    NVRAM on the server board. It allows the User to select which supported chassis (Intel or Non-Intel) and platform chassis configuration is being used. Based on the input provided, the FRUSDR writes sensor data specific to the configuration to NVRAM for the BMC controller to read each time the system is powered on.
  • Page 70 Note: Fan speed control for non-Intel chassis, as configured after running the FRUSDR utility and selecting the Non-Intel Chassis option, is limited to only the CPU fans. The BMC only requires the processor thermal sensor data ito determine how fast to operate these fans. The remaining system fans will operate at 100% operating limits due to unknown variables associated with the given chassis and its fans.

  • Page 71: Flash Rom

    The flash ROM contains system initialization routines, setup utility, and runtime support routines. The exact layout is subject to change, as determined by Intel. A 128 KB block is available for storing OEM code (user binary) and custom logos.

  • Page 72: Bios Setup Utility

    The BIOS Setup utility has the following features: Localization. BIOS Setup uses the Unicode standard and is capable of displaying Setup pages in all languages currently included in the Unicode standard. However, the Intel Server Board BIOS is available only in English.

  • Page 73: Figure 5. General Bios Screen Display Layout

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Figure 5. General BIOS Screen Display Layout Revision 1.1 Intel order number D38960-004...

  • Page 74: Table 13. Bios Setup Page Layout

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet Table 13. BIOS Setup Page Layout Functional Area Description Title Bar The title bar is located at the top of the screen and displays the title of the form (page) the user is currently viewing. It may also display navigational information.

  • Page 75: Table 14. Bios Setup: Keyboard Command Bar

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS The keyboard command bar supports the following: Table 14. BIOS Setup: Keyboard Command Bar Option Description <Enter> Execute The <Enter> key is used to activate sub-menus when the selected feature is a sub-...

  • Page 76: Server Platform Setup Screens

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet 3.7.1.4 Menu Selection Bar The menu selection bar is located at the top of the screen. It displays the major menu selections. 3.7.2 Server Platform Setup Screens The sections below describe the screens available for the configuration of a server platform. In these sections, tables and figures are used to describe the contents of each screen.

  • Page 77: Table 15. Setup Utility - Main Screen Fields

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Table 15. Setup Utility — Main Screen Fields Setup Item Options Help Text Comment BIOS Version No entry allowed Information only. Displays the BIOS version. yy = major version xx = minor version...

  • Page 78: Figure 7. Setup Utility - Advanced Screen Display

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet 3.7.2.1 Advanced Screen The Advanced screen provides an access point to choose to configure several options. On this screen, the user selects the option that is to be configured. Configurations are performed on the selected screen, not directly on the Advanced screen.

  • Page 79: Figure 8. Setup Utility - Processor Configuration Screen Display

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS 3.7.2.1.1 Processor Screen The Processor screen provides a place for the user to view the processor core frequency, system bus frequency, and enable or disable several processor options. The user can also select an option to view information about a specific processor.

  • Page 80: Figure 9. Setup Utility - Specific Processor Information Screen Display

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet Setup Item Options Help Text Comment Execute Disable Bit When disabled, forces the XD Enable feature flag to always return 0 Disable Hardware Prefetcher Enable or disable the hardware Enable...

  • Page 81: Figure 10. Setup Utility - Memory Configuration Screen Display

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Table 17. Setup Utility — Specific Processor Information Screen Fields Setup Item Options Help Text Comment Processor Family No entry allowed Identifies family or generation of the processor. Information only.

  • Page 82: Table 18. Setup Utility - Memory Configuration Screen Fields

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet Table 18. Setup Utility — Memory Configuration Screen Fields Setup Item Options Help Text Comment Total Memory No entry allowed Information only. The amount of memory available in the system in the form of installed FBDIMMs, in units of MB or GB.

  • Page 83: Figure 11. Setup Utility - Ide Controller Configuration Screen Display

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Setup Item Options Help Text Comment DIMM # No entry allowed Displays the state of each DIMM socket present on the board. Each DIMM socket field reflects one of the following possible...

  • Page 84: Table 19. Setup Utility - Ide Controller Configuration Screen Fields

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet Table 19. Setup Utility — IDE Controller Configuration Screen Fields Setup Item Option Help Text Comment Onboard PATA Enable Help: Onboard PATA Controller Controller Disable Onboard SATA Enable Help: Onboard SATA...
  • Page 85 Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Setup Item Option Help Text Comment AHCI Mode Enable Help: AHCI Mode Unavailable if the SATA mode is “Legacy” or if RAID Mode is Disable selected. If AHCI is enabled, no information...

  • Page 86: Figure 12. Setup Utility - Mass Storage Configuration Screen Display

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet 3.7.2.1.4 Mass Storage Screen The Mass Storage screen provides fields to configure when a SAS controller is present on the ® baseboard, mid-plane or backplane of an Intel system. To access this screen from the Main menu, select Advanced | Mass Storage.

  • Page 87: Figure 13. Setup Utility - Serial Port Configuration Screen Display

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Setup Item Option Help Text Comment ® ® Enable Intel Enable If enabled, initialize RAID On Unavailable if the Intel RAID Key is SROMBSAS18E MotherBoard (ROMB). not present. Disable WARNING: Before changing modes, back up array data and delete existing arrays, if any.

  • Page 88: Figure 14. Setup Utility - Usb Controller Configuration Screen Display

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet Table 21. Setup Utility — Serial Ports Configuration Screen Fields Setup Item Option Help Text Comment COM1 Enabled Enables or disables COM1 port. Enable Disabled Address 3F8h Selects the base I/O address for COM1.

  • Page 89: Table 22. Setup Utility - Usb Controller Configuration Screen Fields

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Table 22. Setup Utility — USB Controller Configuration Screen Fields Setup Item Option Help Text Comment USB Devices Shows the number of USB devices in system Information only Enabled: USB Controller...

  • Page 90: Figure 15. Setup Utility - Pci Configuration Screen Display

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet 3.7.2.1.7 PCI Screen The PCI Screen provides fields to configure PCI add-in cards, the onboard NIC controllers, and video options. To access this screen from the Main screen, select Advanced | PCI.

  • Page 91: Figure 16. Setup Utility - System Acoustic And Performance Configuration Screen Display

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Setup Item Option Help Text Comment NIC 2 MAC Address No entry Information only. 12 hex allowed digits of the MAC address. ® IO Acceleration Tech Enabled Enabled or Disable the Intel I/O Acceleration Technology feature of the onboard NICs.

  • Page 92: Figure 17. Setup Utility - Security Configuration Screen Display

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet Table 24. Setup Utility — System Acoustic and Performance Configuration Screen Fields Setup Item Option Help Text Comment Set Fan Profile Performance Select the fan control profile that will be Performance mode favors used to cool the system.

  • Page 93: Table 25. Setup Utility - Security Configuration Screen Fields

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Table 25. Setup Utility — Security Configuration Screen Fields Setup Item Option Help Text Comment Administrator Password Installed Indicates the status of Information only. Disabled if the administrator password. password is blank.

  • Page 94: Figure 18. Setup Utility - Server Management Configuration Screen Display

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet 3.7.2.3 Server Management Screen The Server Management screen provides fields to configure several server management features. It also provides an access point to the screens for configuring console redirection and displaying system information.

  • Page 95: Figure 19. Setup Utility - Console Redirection Screen Display

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Setup Item Option Help Text Comment O/S Boot Watchdog 5 minutes O/S Boot Watchdog Timer Timeout Timer Timeout 10 minutes 15 minutes 20 minutes Console Redirection See section 0 System Information See section 0 3.7.2.3.1...

  • Page 96: Figure 20. Setup Utility - Server Management System Information Screen Display

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet Setup Item Option Help Text Comment Baud Rate 9600 Sets the communication speed for the redirection data 19.2K 36.4K 57.6K 115.2K Terminal Type VT100 Sets the character formatting for the console...

  • Page 97: Figure 21. Setup Utility - Error Manager Screen Display

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Table 28. Setup Utility — Server Management System Information Fields Setup Item Option Help Text Comment Board Part Number Information Only Board Serial Number Information Only System Part Number Information Only...

  • Page 98: Figure 22. Setup Utility - Exit Screen Display

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet 3.7.2.6 Exit Screen The Exit screen allows the user to choose to save or discard the configuration changes made on the other screens. It also provides a method to restore the server to the factory defaults or to save or restore a set of user defined default values.

  • Page 99: Loading Bios Defaults

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Loading BIOS Defaults Different mechanisms exist for resetting the system configuration to the default values. When a request to reset the system configuration is detected, the BIOS loads the default system configuration values during the next POST.

  • Page 100: Password Protection

    3.10 BIOS Update Flash Procedures 3.10.1 Intel Iflash32 BIOS Update Utility The Intel Iflash32 BIOS Update Utility is designed to update the system BIOS in a DOS environment. Boot to the ROM-DOS shell and copy IFlash32.exe and the BIOS binary file (also referred as capsule file) to a DOS bootable diskette, CD or disk-on-key.

  • Page 101: Intel ® One Boot Flash Update Utility

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS ® 3.10.2 Intel One Boot Flash Update Utility ® The Intel One Boot Flash Update utility is run by executing the flashupdt command from a command prompt. In order to run this utility, you must first set the working directory to the directory where the utility is installed.
  • Page 102 One Boot Flash Update utility from a Linux operating system, do the following: 1. Log in as root. 2. Open a terminal and change the working directory to the Intel® One Boot Flash Update utility installation directory: cd /usr/local/flashupdt 3. Execute the following command: /uninstall Revision 1.1...

  • Page 103: Bios Bank Select And One Boot Flash Update

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS 3.11 BIOS Bank Select and One Boot Flash Update One Boot Flash Update refers to the ability to update the BIOS while the server is online and operating. The BIOS Bank Select feature provides the ability to update the BIOS in a fault tolerant way. If the updated (new) BIOS is found to be non functional for any reason, the system can still be booted by rolling back to the previous, healthy BIOS.

  • Page 104: Bios Bank Select Jumper In Bank 0 Mode (Jumper Pins 1 - 2 Connected)

    The OEM FV can include the OEM splash logo and may be updated using the Change Logo utility. If an OEM logo is located in the firmware volume, it is used in place of the standard Intel logo. The logo file can be identified based on the file name.

  • Page 105: Server Managment Boot Device Control

    Intel Corporation and Microsoft Corporation co-author design guides for system designers who will use Intel processors and Microsoft operating systems. The Hardware Design Guide for Microsoft Windows 2000 Server, Version 3.0 is intended for systems that are designed to work with Windows Server class operating systems.

  • Page 106: Front Control Panel Support

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet ® Note: S3 is only supported on the Intel Workstation Board S5000XVN. See the server or workstation Technical Product Specification that applies to your product for more information about the supported sleep states.

  • Page 107: Non-Maskable Interrupt (Nmi) Button

    ACPI S4 (hibernate) state ACPI S5 (soft-off) state ® Note: The S3 state is only supported on the Intel Workstation Board S5000XVN. See the server or workstation Technical Product Specification that applies to your product for more information about supported sleep states.

  • Page 108: Non-Maskable Interrupt Handling

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet 3.17 Non-Maskable Interrupt Handling Non-maskable interrupts are generated by two sources: by a front panel NMI button press or by the BIOS to halt the system upon detecting a system fatal error. The BIOS installs a default NMI handler that displays a system error message and then halts the system.

  • Page 109: Console Redirection

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS 3.20 Console Redirection The BIOS supports redirection of both video and keyboard via a serial link (serial port). When console redirection is enabled, the local (host server) keyboard input and video output are passed both to the local keyboard and video connections, and to the remote console through the serial link.

  • Page 110: Limitations

    Microsoft Windows 2003* WHQL requirements for headless operation of servers. It also maintains a necessary degree of backward compatibility with existing Intel server BIOS products and meets the architectural requirements of Intel server products in development.

  • Page 111: Wired For Management (Wfm)

    Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS Output is displayed locally at the computer on video display devices. This is limited to VGA displays in text or graphics mode. Local input may come from a USB keyboard. Mouse support is not available.

  • Page 112: System Management Bios (Smbios)

    System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet 3.23 System Management BIOS (SMBIOS) The BIOS provides support for the System Management BIOS Reference Specification, Version 2.4 to create a standardized interface for manageable attributes that are expected to be supported by DMI-enabled computer systems.

  • Page 113: System Management

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management System Management Feature Support ® This section provides a high-level list of management features supported by the Intel 631xESB / 632xESB I/O Controller Hub BMC. 4.1.1 Legacy Features These features are carried over from previous platforms with little or no change in functionality.
  • Page 114 NMI – Provides commands to set/get NMI source. Supports generation of NMI due to watchdog timer, IPMI command, or front panel NMI button. Monitors system NMI signal. ® ARPs – The BMC can send and respond to ARP. This is supported on Intel 631xESB / 632xESB I/O Controller Hub embedded NICs ®...

  • Page 115: New Features

    System Management 4.1.2 New Features ® This section lists features that are being introduced on server boards that use the Intel 5000 Series Chipsets. Acoustic management – Improved acoustic levels are achieved by including support for fan profiles using TControl ver2 SDRs.

  • Page 116: Figure 23. Intel 631Xesb / 632Xesb I/O Controller Hub Power / Reset Signals

    System Management Intel® 5000 Series Chipsets Server Board Family Datasheet The following is a simplified block diagram showing the power and reset signal interconnections ® to the Intel 631xESB / 632xESB I/O Controller Hub. ® Figure 23. Intel 631xESB / 632xESB I/O Controller Hub Power / Reset Signals Revision 1.1...

  • Page 117: Bmc Reset Control

    (BSP) fails. The intent of the FRB algorithms is to detect BSP failure, disable the failed ® processor, and reset the server with a different processor as the BSP. For Intel 5000 platforms, only FRB2 is supported using watchdog timer commands.
  • Page 118 System Management Intel® 5000 Series Chipsets Server Board Family Datasheet 4.4.1.3 Watchdog Timer Timeout Reason Bits To implement FRB2, during POST the BIOS determines whether a BMC watchdog timer timeout occurred on the previous boot attempt. If it finds a watchdog timeout did occur, it determines whether that timeout was an FRB2 timeout, system management software (SMS) timeout, or an intentional, timed hard reset.

  • Page 119: Integrated Front Panel User Interface

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management Integrated Front Panel User Interface The BMC incorporates the front panel interface functionality and supports an SSI EB compliant model. Indicators on supported front panels are LEDs. 4.5.1 Power LED The green power LED is active when system DC power is on.

  • Page 120: Table 36. System Status Led Indicator States

    System Management Intel® 5000 Series Chipsets Server Board Family Datasheet The following table maps the platform state to the LED state. Table 36. System Status LED Indicator States Color State Criticality Description Not ready AC power off Green / Alternating Not ready Pre DC power on –...

  • Page 121: Chassis Id Led

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management 4.5.3 Chassis ID LED The chassis ID LED provides a visual indication of a system being serviced. It is toggled by the chassis ID button Table 37. Chassis ID LED Indicator States...

  • Page 122: Front Panel Lock-Out Operation

    System Management Intel® 5000 Series Chipsets Server Board Family Datasheet 4.5.4.3 Reset Button An assertion of the front panel reset signal to the BMC causes the system to start the reset and reboot process, as long as the BMC has not locked-out this input. This assertion is immediate and without the cooperation from software or the operating system.

  • Page 123: Private Management I 2 C Buses

    The NMI / diagnostic interrupt specified for an IPMI 2.0 watchdog timer is associated with an NMI on IA-32 platforms. A watchdog pre-timeout SMI (or equivalent signal assertion) is ® not supported on platforms that use one of the Intel 5000 Series Chipsets. System Event Log (SEL) The BMC implements the logical system event log as specified in the Intelligent Platform Management Interface Specification, Version 2.0.

  • Page 124: Servicing Events

    ® Intel 5000 Series Chipsets’ ICH component, not on the component in the SIO that the BMC uses to initialize its clock. As a result, it is possible for synchronization issues to exist between the BMC clock and the real-time clock. In some situations, the BIOS updates the BMC clock.

  • Page 125: Sensor Data Record (Sdr) Repository

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management Sensor Data Record (SDR) Repository The BMC implements the logical sensor data record (SDR) repository as specified in the Intelligent Platform Management Interface Specification, Version 2.0 The SDR repository is accessible via all communication transports.

  • Page 126: Diagnostics And Beep Code Generation

    Codes that are common across all platforms that use one of the Intel 5000 Series Chipsets are listed in the following table. Each digit in the code is represented by a sequence of beeps whose count is equal to the digit.

  • Page 127: Signal Generation

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management 4.12.1 Signal Generation The BMC generates an NMI pulse under certain conditions. The BMC-generated NMI pulse duration is at least 30 ms. After an NMI has been generated by the BMC, the BMC will not generate another until the system has been reset or powered down.

  • Page 128: Processor Status Sensors

    BIOS Configuration error (for instance, stepping mismatch) BIOS Processor presence detected ® Note 1: A fault is not reflected in the processor status sensor on platforms that use one of the Intel 5000 Series Chipsets 4.13.1.1 Processor Presence When the BMC detects an empty processor socket, it sets the disable bit in the processor status for that socket and clears the remaining status bits, including any persistent bits.

  • Page 129: Thermtrip Monitoring

    0 degrees C. PECI sensor name: The PECI sensors are called Px Therm Margin on Intel S5000 systems, where the 'x' is the processor #. Example: Processor 1 would read P1 Therm Margin.

  • Page 130: Ierr Monitoring

    %. This is a standard method in IPMI to determine if a sensor is read as a %. PROCHOT sensor name: The PROCHOT sensors are called Px Therm Ctrl % on Intel S5000 systems, where 'x' is the processor #. Example: Processor 1 would read P1 Therm Ctrl %.

  • Page 131: Processor Thermal Control Monitoring (Prochot)

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management 4.13.9 Processor Thermal Control Monitoring (Prochot) The BMC monitors processor thermal control monitoring for each processor. This functionality is provided by the National Semiconductor* LM94 system management controller device, which provides a reading of the percentage of time that the processor ProcHot signal is asserted over a given measurement window.

  • Page 132: Standard Fan Management

    System Management Intel® 5000 Series Chipsets Server Board Family Datasheet 4.14 Standard Fan Management The BMC controls and monitors the system fans. For each fan, there is a fan speed sensor that provides fan failure detection. Some platforms also provide fan presence detection which the BMC maps into per-fan presence sensors.

  • Page 133: Nominal Fan Speed

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management 4.14.1 Nominal Fan Speed It is possible to configure a fan domain’s Nominal fan speed to be either static (fixed value) or controlled by the state of one or more associated temperature sensors.

  • Page 134: Clamp

    System Management Intel® 5000 Series Chipsets Server Board Family Datasheet 4.14.2.2 Domain Maximum Stepwise Linear T sub-records might have a flag set that indicates that the instance CONTROL provides the fan domain maximum PWM value. These sub-records do not contribute to the fan speed as described above.

  • Page 135: Hot Swap Fan Support

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management 4.14.6 Hot Swap Fan Support Some chassis and server boards provide support for hot-swap fans. These fans can be removed and replaced while the system is operating normally. The BMC implements fan presence sensors for each hot swappable fan.

  • Page 136: System Memory Ras And Bus Error Monitoring

    System Management Intel® 5000 Series Chipsets Server Board Family Datasheet 4.17 System Memory RAS and Bus Error Monitoring System memory and bus error monitoring is done by the system BIOS. At startup, the BIOS checks the chipset for any memory errors early in the boot process. The BIOS updates the status of RAS configuration at startup and later at run time.

  • Page 137: Critical Interrupt Sensor

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management 4.17.3 Critical Interrupt Sensor The BMC implements a Critical Interrupt (13h) sensor for reporting the following conditions / events: Bus Uncorrectable Error: Only sensed after an SMI timeout (post-mortem) Front Panel NMI / diagnostic interrupt: Monitored during normal system operation 4.17.4...

  • Page 138: System Memory Redundancy Monitoring

    ® The Intel 5000 Series Chipsets support memory redundancy features that go beyond single bit error correction, allowing failing or failed DIMMs to be managed on-line without affecting normal system operation. BMC support for these is indicated in the following sections.
  • Page 139 Intel® 5000 Series Chipsets Server Board Family Datasheet System Management 4.17.5.1 DIMM Sparing With DIMM sparing, the BMC will implement two sensors per DIMM sparing domain (the set of DIMMs which share a spare set of DIMMs). Each sparing domain will have an associated unique Entity ID.
  • Page 140 System Management Intel® 5000 Series Chipsets Server Board Family Datasheet 4.17.5.2 Memory Mirroring If a specific platform supports memory mirroring, the BMC will implement two sensors per memory mirroring domain (the DIMMs that form a mirrored set). Each mirroring domain will have an associated unique entity ID.

  • Page 141: System Memory Monitoring And System Boot

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management 4.17.6 System Memory Monitoring and System Boot The following sequence of events describes the system booting process with respect to the system memory monitoring feature. During system boot, BIOS will determine the DIMM population and set this state in the BMC.

  • Page 142: Field Replaceable Unit (Fru) / Fault Led Control

    The server board BMC supports a set of commands for setting and retrieving configuration ® information related to the server board support for the Intel RMM. These commands are primarily used by the add-in card when power is first applied to the card. They query the BMC to discover platform support for the add-in connector.

  • Page 143: Division Of Network Traffic

    Server management network traffic is handled either by the Intel RMM or by the BMC, depending on the physical configuration. This is described in the two sub-sections below. The ® BMC only handles IPMI-over-LAN traffic, including SOL traffic, even if no Intel RMM is ® installed. The Intel RMM handles TCP/IP traffic.

  • Page 144: Serial Routing

    When BMC SEL events are generated through any mechanism other than the Add SEL Entry ® command, the BMC will send time-stamped copies of these events to the Intel RMM). Events are forwarded even if the BMC’s SEL is full.

  • Page 145: Channel Management

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management These specifications are defined in the following sub-sections. Section 4.26 talks about basic characteristics of the communication protocols used in all of the above interfaces. 4.22 Channel Management Every messaging interface is assigned an IPMI channel ID by IPMI 2.0. Commands are provided to configure each channel for privilege levels and access modes.

  • Page 146: Host To Bmc Communication Interface

    System Management Intel® 5000 Series Chipsets Server Board Family Datasheet 4.26 Host to BMC Communication Interface 4.26.1 LPC / KCS Interface The BMC has three 8042 keyboard controller style (KCS) interface ports as described in the IPMI 2.0 specification. These interfaces are mapped into the host I/O space and accessed via the chipset low pin count (LPC) bus.

  • Page 147: Ipmb Communication Interface

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management 4.27 IPMB Communication Interface The IPMB is a communication protocol that utilizes the 100 KB/s version of an I C bus as its physical medium. For more information on I...

  • Page 148: Ipmb Lun Routing

    System Management Intel® 5000 Series Chipsets Server Board Family Datasheet 4.27.3 IPMB LUN Routing The BMC can receive either request or response IPMB messages. The treatment of these messages depends on the destination logical unit number (LUN) in the IPMB message. For IPMB request messages, the destination LUN is the responder’s LUN.

  • Page 149: Figure 25. Bmc Ipmb Message Reception

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management Figure 8 shows a logical block diagram of the BMC receiving IPMB messages. IPMB I2C INTERFACE IPMB MSG VERIFICATION LUN ROUTING LUN=00b LUN=10b (BMC) (SMS) BMC IPMB Other BMC RECEIVE...

  • Page 150: Emergency Management Port (Emp) Interface

    Intel® 5000 Series Chipsets Server Board Family Datasheet 4.28 Emergency Management Port (EMP) Interface The EMP interface is the Intel implementation of the IPMI 2.0 IPMI over serial feature. The primary goal of providing an out-of-band RS232 connection is to give system administrators the ability to access low-level server management firmware functions by using commonly available tools.

  • Page 151: Table 45. Terminal Mode Commands

    Intel® 5000 Series Chipsets Server Board Family Datasheet System Management 4.28.3.1 Input Restrictions 4.28.3.1.1 Maximum Input Length The BMC supports a maximum of 122 characters per line. The BMC will stop accepting new characters and stop echoing input when the 122-character limit is reached. However, selected characters will continue to be accepted and handled appropriately even after the character limit is reached.

  • Page 152: Invalid Password Handling

    System Management Intel® 5000 Series Chipsets Server Board Family Datasheet 4.28.3.2.2 Text Command Privilege Levels The BMC supports the privilege level scheme for terminal mode text commands as specified in Table 45. 4.28.3.3 Bridging Support The BMC supports the optional bridging functionality described in the IPMI 2.0 specification.

  • Page 153: Lan Interface

    Two of the LAN interfaces utilize the embedded Intel 631xESB / 632xESB I/O Controller Hub NICs (one channel per embedded NIC). ® One LAN interface utilizes an optional external NIC known as the Intel RMM NIC. This ® NIC requires the presence of the optional Intel Remote Management Module add-in card.

  • Page 154: Ipmi 2.0 Messaging

    System Management Intel® 5000 Series Chipsets Server Board Family Datasheet 4.29.2 IPMI 2.0 Messaging IPMI 2.0 messaging is built over RMCP+ and has a different session establishment protocol. The session commands are defined by RSSP and implemented at the RMCP+ level, not IPMI commands.

  • Page 155: Intel ® 631Xesb / 632Xesb I/O Controller Hub Embedded Lan Channels

    Intel® 5000 Series Platforms that use the Chipset do not support the previous generation Intel proprietary SOL, now known as SOL 1.0. IPMI 2.0 introduces a standard serial-over-LAN feature, which is implemented as a standard payload type (01h) over RMCP+.

  • Page 156: Error Reporting And Handling

    Management. Fault Resilient Booting (FRB) Fault resilient booting (FRB) is feature that Intel provides to detect and handle errors during the system boot process. FRB helps to make sure the system boots, even if one or more processors fail during POST. There are several possible failures during the booting process that...

  • Page 157: Error Handling And Logging

    Intel® 5000 Series Chipsets Server Board Family Datasheet Error Reporting and Handling Error Handling and Logging This section defines how errors are handled by the system BIOS, including a discussion of the role of the BIOS in error handling and the interaction between the BIOS, platform hardware, and server management firmware with regard to error handling.

  • Page 158: Timestamp Clock Event

    Error Reporting and Handling Intel® 5000 Series Chipsets Server Board Family Datasheet 5.2.2.3 Processor Bus Error The BIOS enables the error correction and detection capabilities of the processors by setting appropriate bits in the processor model specific register (MSR) and the appropriate bits in the chipset.

  • Page 159: Error Messages And Error Codes

    Intel® 5000 Series Chipsets Server Board Family Datasheet Error Reporting and Handling Error Messages and Error Codes The system BIOS displays error messages on the screen. Before video initialization, beep codes inform the user of errors. POST error codes are logged in the event log. The BIOS displays POST error codes on the screen.

  • Page 160: Post Code Checkpoints

    Error Reporting and Handling Intel® 5000 Series Chipsets Server Board Family Datasheet A. Status LED D. Bit 1 LED (POST LED) B. ID LED E. Bit 2 LED (POST LED) C. MSB LED (POST LED) F. LSB LED (POST LED) Figure 26.
  • Page 161 Intel® 5000 Series Chipsets Server Board Family Datasheet Error Reporting and Handling Diagnostic LED Decoder Description Checkpoint G=Green, R=Red, A=Amber Bit 1 Bit 2 0x53h Reserved for PCI bus 0x54h Reserved for PCI bus 0x55h Reserved for PCI bus 0x56h...
  • Page 162 Error Reporting and Handling Intel® 5000 Series Chipsets Server Board Family Datasheet Diagnostic LED Decoder Description Checkpoint G=Green, R=Red, A=Amber Bit 1 Bit 2 0xBAh Detecting presence of a removable media device (IDE CDROM detection, etc.) 0xBCh Enabling / configuring a removable media device...

  • Page 163: Post Error Messages And Handling

    Intel® 5000 Series Chipsets Server Board Family Datasheet Error Reporting and Handling Diagnostic LED Decoder Description Checkpoint G=Green, R=Red, A=Amber Bit 1 Bit 2 Pre-EFI Initialization Module (PEIM) / Recovery 0x30h Crisis recovery has been initiated because of a user request...
  • Page 164 Error Reporting and Handling Intel® 5000 Series Chipsets Server Board Family Datasheet Error Code Error Message Response 8161 Processor 02 unable to apply BIOS update Pause 8190 Watchdog timer failed on last boot Pause 8198 Operating system boot watchdog timer expired on last boot...

  • Page 165: Post Error Beep Codes

    Intel® 5000 Series Chipsets Server Board Family Datasheet Error Reporting and Handling Error Code Error Message Response 858C DIMM_D1 Correctable ECC error encountered. Pause 858D DIMM_D2 Correctable ECC error encountered. Pause 858E DIMM_D3 Correctable ECC error encountered. Pause 858F DIMM_D4 Correctable ECC error encountered.

  • Page 166: Glossary

    Glossary Intel® 5000 Series Chipsets Server Board Family Datasheet Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (e.g., “82460GX”) with alpha entries following (e.g., “ACPI”). Acronyms are then entered in their respective place, with non-acronyms following.
  • Page 167 Intel® 5000 Series Chipsets Server Board Family Datasheet Glossary Term Definition ICMB Intelligent Chassis Management Bus IERR Internal Error I/O and Firmware Bridge INTR Interrupt Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface Infrared In-Target Probe...
  • Page 168 Glossary Intel® 5000 Series Chipsets Server Board Family Datasheet Term Definition 5000 The chipset used in the server board. SECC Single Edge Connector Cartridge SEEPROM Serial Electrically Erasable Programmable Read-Only Memory System Event Log Server Input/Output Server Management Interrupt (SMI is the highest priority nonmaskable interrupt)

  • Page 169: Reference Documents

    Platform Management FRU Information Storage Definition, Version 1.0. 1998. Intel Corporation, Hewlett-Packard Company, NEC Corporation, Dell Computer Corporation. http://developer.intel.com/design/servers/ipmi/spec.htm Server Power Control White Paper, Revision 0.93. November 5, 1998. Intel Corporation. The SMBus Specification, Intel Corporation Processor Application Note AP-485 Intel Processor Identification and the CPUID Function.
  • Page 170 Reference Documents Intel® 5000 Series Chipsets Server Board Family Datasheet PCI Local Bus Specification, Revision 2.2, http://www.pcisig.org/ PCI to PCI Bridge Specification, Revision 1.1, http://www.pcisig.org/ PCI BIOS Specification, Revision 2.1, http://www.pcisig.org/ PCI Power Management Specification, Revision 1.0, http://www.pcisig.org/ PCI IRQ Routing Table Specification, Revision 1.0, Microsoft Corporation.

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