Intel E7500 Chipset - Intel SE7500CW2 Technical Product Specification

Functional Architecture
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3.1.2.3 I C Bus
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The I C bus is used by the system BIOS to retrieve DIMM information needed to program the
MCH memory registers which are required to boot the system.
3.1.2.4 DRAM ECC
The ECC used for DRAM provides chipkill technology protection for x4 SDRAM modules. DRAM
modules that are x8 use the same algorithm but will not have chipkill technology protection, since
at most only four bits can be corrected with this ECC.
3.2

Intel E7500 Chipset

The Intel Server Board SE7500CW2 is designed around the Intel E7500 chipset. The chipset
provides an integrated I/O bridge and memory controller, and a flexible I/O subsystem core (PCI-
X). This is targeted for multiprocessor systems and standard high-volume servers. The Intel
E7500 chipset consists of three components:
•
MCH: Memory Control Hub North Bridge. The MCH North Bridge accepts access
requests from the host (processor) bus and directs those accesses to memory or to one
of the PCI buses. The MCH monitors the host bus, examining addresses for each
request. Accesses may be directed to a memory request queue for subsequent
forwarding to the memory subsystem, or to an outbound request queue for subsequent
forwarding to one of the PCI buses. The MCH also accepts inbound requests from the
P64H2 and the ICH3-S. The MCH is responsible for generating the appropriate controls to
control data transfer to and from memory.
•
P64H2: PCI-X 64bit Hub 2.0 I/O Bridge. The P64H2 provides the interface for two 64-
bit, 133-MHz Rev. 2.2 compliant PCI-X buses (implemented on Intel
SE7500CW2 as one bus with one 64-bit, 133MHz slot and one bus with two 64-bit,
100MHz slots). The P64H2 is both master and target on both PCI-X buses.
•
ICH3-S: IO Control Hub South Bridge. The ICH3-S controller has several
components. It provides the interface for a 32-bit, 33-MHz Rev. 2.2-compliant PCI bus.
The ICH3-S can be both a master and a target on that PCI bus. The ICH3-S also includes
a USB controller and an IDE controller. The ICH3-S is also responsible for much of the
power management functions, with ACPI control registers built in. The ICH3-S also
provides a number of GPIO pins and has the LPC bus to support low speed legacy I/O.
The MCH, P64H2, and ICH3-S chips provide the pathway between processor and I/O systems.
The MCH is responsible for accepting access requests from the host (processor) bus, and
directing all I/O accesses to one of the PCI buses or legacy I/O locations. If the cycle is directed
to one of the 64-bit PCI segments, the MCH communicates with the P64H2 through a private
interface called the HI (Hub Interface). If the cycle is directed to the ICH3-S, the cycle is output on
the MCH's 8bit HI 1.5 bus. The P64H2 translates the HI 2.0 bus operation to a 64-bit PCI Rev.
2.1-compliant signaling environment operating at from 133MHz to 33 MHz.
The HI 2.0 bus is 16 bits wide and operates at 66 MHz with 512MT/s, providing over 1 GB per
second of bandwidth.
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Revision 1.40
SE7500CW2 Server Board Technical Product Specification
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Server Board