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System BIOS
Beginning at the lowest device, the BIOS uses a "depth-first" scan algorithm to enumerate the
PCI buses. Each time a bridge device is located, the bus number is incremented and scanning
continues on the secondary side of the bridge until all devices on the current bus are scanned.
The BIOS then scans for PCI devices using a "breadth-first" search. All devices on a given bus
are scanned from lowest to highest before the next bus number is scanned.
The system BIOS POST maps each device into memory
2
channels
as required. The BIOS programs the PCI-ISA interrupt routing logic in the chipset
hardware to steer PCI interrupts to compatible ISA IRQs.
The BIOS dispatches any option ROM code for PCI devices to the DOS compatibility hole
3
(C0000h to E7FFFh
) and transfers control to the entry point. Because the DOS compatibility
hole is a limited resource, system configurations with a large number of PCI devices may
encounter a shortage of this resource. If the BIOS runs out of option ROM space, some PCI
option ROMs are not executed and a POST error is generated. Drivers and/or the OS can detect
installed devices and determine resource consumption using the defined PCI, legacy PnP BIOS,
and/or ACPI BIOS interface functions.
The non-volatile RAM (NVRAM) API and the PCI data records are not supported by the system
BIOS. The configuration information of the PCI devices is stored in ESCD.
6.2.4
Legacy ISA Configuration
Legacy ISA add-in devices are not supported.
6.2.5
Automatic Detection of Video Adapters
The BIOS detects video adapters in the following order:
1. Off-board PCI or an external device.
2. On-board PCI or the onboard ATI Rage XL component.
The on-board (or off-board) video BIOS is shadowed, starting at address C0000h, and is
initialized before memory tests begin in POST. Precedence is always given to off-board devices.
No BIOS <F2> switch is present to disable external PCI devices. Though no switch exists in
BIOS the onboard device will automatically be disabled if an add-in video card is added
according to the order mentioned above.
6.2.6
Keyboard / Mouse Configuration
The BIOS will supports both a mouse and keyboard attached to the PS/2 connectors at the I/O
panel on the board. The use of each device is detected during POST and the KBC is
1
The BIOS does not support devices behind PCI-to-PCI bridges that require mapping to the first 1 MB of memory
space due to PCI architectural limitations (refer to the PCI-to-PCI Bridge Architecture Specification).
2
PCI IRQ assignments may be overridden using the System Setup Utility.
3
Note that the BIOS size may increase thereby limiting the area used by option ROMs to 0C0000h – 0E0000h.
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Revision 1.40
SE7500CW2 Server Board Technical Product Specification
1
and/or I/O space, and assigns IRQ
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