Mch Memory Architecture Overview; Table 3. Supported Ddrs - Intel SE7500CW2 Technical Product Specification

SE7500CW2 Server Board Technical Product Specification
All I/O for the Intel Server Board SE7500CW2, including PCI and PC-compatible, is directed
through the MCH and then through either the P64H2 or the ICH3-S provided PCI buses.
•
The ICH3-S provides a 32-bit/33-MHz PCI bus hereafter called P32-A.
•
The P64H2 provides two independent 64-bit, 133-MHz PCI-X buses hereafter called P64-
B, and P64-C.
This independent bus structure allows all three PCI buses to operate independently.
3.2.1

MCH Memory Architecture Overview

The MCH supports a 144-bit Memory Sub-system that can support a maximum of 4GB
2GB DIMMs). This configuration needs external registers for buffering the memory address and
control signals. In this configuration MCH support four DDR-200 compliant registered for
1
maximum of 8GB . The four chip selects are registered inside MCH and need no external
registers for chip selects.
The memory interface runs at 200MT/s. The Memory interface supports a 144-bit wide memory
array. It uses fifteen address lines (BA[1:0] and MA[12:0]) and supports 64Mb, 128Mb, 256Mb,
512Mb DRAM densities. The DDR DIMM interface supports memory scrubbing, single-bit error
correction, and multiple bit error detection and chip kill with x4 DIMMs .
3.2.1.1 DDR Configurations
The DDR interface supports up to 4GB
density DIMMs. The DDR can be any industry-standard DDR. The following table shows the
DDR DIMM supported.
DIMM
Capacity Organization
128MB 16M x 72
128MB 16M x 72
128MB 16M x 72
256MB 32M x 72
256MB 32M x 72
256MB 32M x 72
256MB 32M x 72
512MB 64M x 72
512MB 64M x 72
1
As of the writing of this document, testing with 2GB DIMM modules was not complete and therefore not yet
supported. 2GB DIMM support would allow for up to 8GB of main memory on the SE7500CW2. For updates on
support of 2GB DIMM modules, visit the SE7500CW2 support website at
http://support.intel.com/support/motherboards/server/se7500cw2.
11
Revision 1.40
1
of main memory and supports single- and double-

Table 3. Supported DDRs

DIMM SDRAM
Density Organization
64Mbit
64Mbit
128Mbit
64Mbit
128Mbit
128Mbit
256Mbit
128Mbit
256Mbit
SDRAM # SDRAM
Devices/rows/Banks
16M x 4 18/1/4
8M x 8 18/2/4
16M x 8 9/1/4
16M x 4 36/2/4
32M x 4 18/1/4
16M x 8 18/2/4
32M x 8 9/1/4
32M x 4 36/2/4
64M x 4 18/1/4
Functional Architecture
1
(using
# Address bits
rows/Banks/column
12/2/10
12/2/9
12/2/10
12/2/10
12/2/11
12/2/10
13/2/10
12/2/11
13/2/11