Intel E7500 Chipset - Intel SE7500WV2 Training Manual

Hide thumbs Also See for SE7500WV2:
Table of Contents

Advertisement

Student Workbook

Intel E7500 Chipset

Intel
Intel E7500 Chipset
• E7500 Memory Controller Hub
• P64H2 PCI Controller Hub
• ICH3 I/O Controller Hub
®
The Intel
Server Board SE7500WV2 is designed around the Intel E7500 chipset, a set of controller chips that support
the core functions of the server board. This chipset utilizes a controller hub architecture and includes the following
components:
E7500 Memory Controller Hub (MCH):
Monitors the processor bus for access requests and directs those requests to memory or to one of the PCI buses
as appropriate
Contains an integrated memory controller that controls data transfers to and from memory and handles error
detection and correction
Provides hub links for both the P64H2 and the ICH3
Accepts inbound requests from the P64H2 and the ICH3 for direction to either the processor subsystem or
memory subsystem
P64H2 PCI Controller Hub:
Connects to the E7500 MCH through a Hub Interface 2.0 bus that provides over 1 GB/s of bandwidth
Provides interfaces to two 64-bit, PCI-X buses
Acts as both a target and a master on the PCI-X buses
ICH3 I/O Controller Hub:
Connects to the E7500 MCH through a Hub Interface 1.5 bus that provides 266 MB/s of bandwidth
Provides the interface for one 32-bit, 33-MHz PCI bus
Acts as both a target and a master on the PCI bus
Integrated PCI bus master ATA-100 IDE controller
Three integrated universal serial bus (USB) controllers
Integrated 16-entry advanced programmable interrupt controller (APIC) to distribute PCI interrupts
Integrated advanced configuration and power interface (ACPI)
Provides a low pin count (LPC) interface connecting to the SuperI/O* controller for floppy, PS/2, COM port
and hardware monitor functions
© 2003 Intel Corporation
®
Server Board SE7500WV2
– Controls processor and memory
data I/O requests
– Controls data I/O requests to
and from PCI subsystem
– Provides interface for two PCI-X
buses
– Provides interface for 32-bit/33-
MHz PCI bus
– Integrated IDE and USB
controllers
– Provides interface to legacy I/O
– Provides many power
management functions
*Other names and brands may be claimed as the property of others.
®
Intel
Server Board SE7500WV2 Training
© 2003 Intel Corporation.
23

Advertisement

Table of Contents
loading

Table of Contents