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Included PCI Devices
4.5.2
APIC Interrupt Routing
For APIC mode, the Intel Server Board SE7500CW2 interrupt architecture incorporates three
Intel I/O APIC devices to manage and broadcast interrupts to local APICs in each processor. The
Intel I/O APICs monitor each interrupt on each PCI device including PCI slots in addition to the
ISA compatibility interrupts IRQ(0-15). When an interrupt occurs, a message corresponding to
the interrupt is sent across a three-wire serial interface to the local APICs. The APIC bus
minimizes interrupt latency time for compatibility interrupt sources. The I/O APICs can also
supply greater than 16 interrupt levels to the processor(s). This APIC bus consists of an APIC
clock and two bi-directional data lines.
4.5.2.1
Legacy Interrupt Sources
The table below recommends the logical interrupt mapping of interrupt sources on the Intel
Server Board SE7500CW2. The actual interrupt map is defined using configuration registers in
the ICH3-S.
ISA Interrupt
INTR
Processor interrupt.
NMI
NMI to processor.
IRQ0
System timer
IRQ1
Keyboard interrupt.
IRQ2
Slave PIC
IRQ3
Serial port 1 or 2 interrupt from SIO device, user-configurable.
IRQ4
Serial port 1 or 2 interrupt from SIO device, user-configurable.
IRQ5
Parallel Port / Generic
IRQ6
Floppy disk.
IRQ7
Parallel Port / Generic
IRQ8_L
Active low RTC interrupt.
IRQ9
SCI*
IRQ10
Generic
IRQ11
Generic
IRQ12
Mouse interrupt.
IRQ13
Floaty processor.
IRQ14
Compatibility IDE interrupt from primary channel IDE devices 0 and 1.
IRQ15
Secondary IDE Cable
SMI*
System Management Interrupt. General purpose indicator sourced by the ICH3-S to the
processors.
4.5.3
Serialized IRQ Support
The Intel® Server Board SE7500CW2 supports a serialized interrupt delivery mechanism.
Serialized Interrupt Requests (SERIRQ) consists of a start frame, a minimum of 17 IRQ / data
channels, and a stop frame. Any slave device in the quiet mode may initiate the start frame.
While in the continuous mode, the start frame is initiated by the host controller.
22
Revision 1.40
SE7500CW2 Server Board Technical Product Specification
Table 8. Interrupt Definitions
Description
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