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AD9843A
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
Register
Address
Name
A0 A1 A2
Operation
0
0
0
VGA Gain
1
0
0
Clamp Level
0
1
0
Control
1
1
0
CDS Gain
0
0
1
Internal use only, must be set to zero.
RNW
0
SDATA
t
DS
SCK
t
LS
SL
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BIT = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
RNW
SDATA
1
t
DS
SCK
t
LS
SL
NOTES:
1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON SCK
FALLING EDGES.
RNW
A0
SDATA
0
0
SCK
1
SL
NOTES:
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING
ONE ADDRESS AT A TIME.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
Table I. Internal Register Map
D0
D1
D2
Channel Select
Power-Down
CCD/AUX
Modes
LSB
LSB
0
0
0
LSB
Should be set to one.
TEST
0
A0
A1
A2
D0
t
DH
TEST
0
A0
A1
A2
D0
t
t
DH
DV
11 BITS
OPERATION
A1
0
0
0
D0
D1
D2
D3
2
3
4
5
6
7
8
Data Bits
D3
D4
D5
Software OB Clamp 0
Reset
On/Off
CDS Gain Clock Polarity Select for
On/Off
SHP/SHD/CLP/DATA
MSB
D1
D2
D3
D4
D5
D1
D2
D3
D4
D5
10 BITS
AGC GAIN
...
...
D10
D0
D1
D2
D3
...
...
9
16
17
18
19
20
D6
D7
D8
1
0
MSB
X
0
0
X
X
X
D6
D7
D8
D9
D10
t
LH
D9
D6
D7
D8
D10
t
LH
8 BITS
10 BITS
CLAMP LEVEL
CONTROL
...
...
D9
D0
D9
D7
D0
...
...
26
27
34
35
44
...
D9
D10
0
0
MSB
X
X
X
Three-
X
State
X
X
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