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D10
D9
D8
D7
0
0
0
1
Must be set to zero.
Set to one.
MSB
D10
D9
D8
X
0
0
1
1
1
1
D10
D9
D8
X
X
X
Data Out
D10
D9
D8
X
0 Enable
0
1 Three-State
Must be set to zero.
When D3 = 0 (CDS Gain Disabled), the CDS Gain Register is fixed at 4 dB (Code 63 dec).
D10
D9
D8
X
X
X
Control Register Bit D3 must be set high for the CDS Gain Register to be used.
Table II. Operation Register Contents (Default Value x000)
Optical Black Clamp
D6
D5
0
0 Enable Clamping
1 Disable Clamping
Table III. VGA Gain Register Contents (Default Value x096)
D7
D6
D5
0
1
0
1
1
1
1
1
1
Table IV. Clamp Level Register Contents (Default Value x080)
MSB
D7
D6
D5
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Table V. Control Register Contents (Default Value x000)
DATACLK
D7
D6
0
0 Rising Edge Trigger
1 Falling Edge Trigger
Table VI. CDS Gain Register Contents (Default Value x000)
MSB
D7
D6
D5
X
X
0
0
1
1
Reset
Power-Down Modes
D4
D3 D2
0 Normal
0
0 Normal Power
1 Reset All
0
1 Fast Recovery
Registers
1
0 Standby
to Default 1
1 Total Power-Down 1
D4
D3
D2
1
1
1
•
•
•
1
1
1
1
1
1
D4
D3
D2
0
0
0
0
0
0
0
0
0
•
•
•
1
1
1
1
1
1
CLP/PBLK
SHP/SHD
D5
D4
0 Active Low
0 Active Low
1 Active High
1 Active High 1 Enabled
D4
D3
D2
0
0
0
•
•
•
1
1
1
0
0
0
•
•
•
1
1
1
AD9843A
Channel Selection
D1 D0
0
0
0
1
1
0
1
LSB
D1
D0
Gain (dB)
1
1
2.0
•
•
•
1
0
35.965
1
1
36.0
LSB
D1
D0
Clamp Level (LSB)
0
0
0
0
1
0.25
1
0
0.5
•
•
•
1
0
63.5
1
1
63.75
CDS Gain
D3
D2
0 Disabled
0
LSB
D1
D0
Gain (dB)
0
0
+4.3
•
•
•
1
0
+10.0
0
0
–2.0
•
•
•
1
1
+4.0
CCD-Mode
AUX1-Mode
AUX2-Mode
Test Only
D1
D0
0
0
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