Analog Devices AD9843A User Manual page 9

CCD-MODE AND AUX-MODE TIMING
CCD
SIGNAL
N
t
ID
SHP
t
S1
SHD
t
INH
DATACLK
t
OD
OUTPUT
N–10
DATA
NOTES:
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
EFFECTIVE PIXELS
CCD
SIGNAL
CLPOB
CLPDM
PBLK
OUTPUT
EFFECTIVE PIXEL DATA
DATA
NOTES:
1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.
VIDEO
SIGNAL
DATACLK
t
OD
OUTPUT
N–10
DATA
N+1
t
ID
t
t
CP
S2
t
H
N–9 N–8
OPTICAL BLACK PIXELS
OB PIXEL DATA
N
N+1
t
ID
t
CP
t
H
N–9 N–8
N+2
HORIZONTAL
BLANKING
DUMMY PIXELS
N+8
N+2
AD9843A
N+9 N+10
N–1 N
EFFECTIVE PIXELS
DUMMY BLACK EFFECTIVE DATA
N+9
N–1 N