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APPLICATIONS INFORMATION
The AD9843A is a complete Analog Front End (AFE) product
for digital still camera and camcorder applications. As shown in
Figure 16, the CCD image (pixel) data is buffered and sent to
the AD9843A analog input through a series input capacitor.
The AD9843A performs the dc restoration, CDS, gain adjust-
ment, black level correction, and analog-to-digital conversion.
The AD9843A's digital output data is then processed by the
image processing ASIC. The internal registers of the AD9843A
—used to control gain, offset level, and other functions—are
programmed by the ASIC or microprocessor through a 3-wire
serial digital interface. A system timing generator provides the
clock signals for both the CCD and the AFE.
Internal Power-On Reset Circuitry
After power-on, the AD9843A will automatically reset all inter-
nal registers and perform internal calibration procedures. This
takes approximately 1 ms to complete. During this time, normal
clock signals and serial write operations may occur. However,
serial register writes will be ignored until the internal reset
operation is completed. Pin 43 (formerly RSTB on the AD9843
non-A) is no longer used for the reset operation. Toggling Pin
43 in the AD9843A will have no effect.
DATA
OUTPUTS
3
SERIAL
INTERFACE
48 47 46 45 44
DRVSS
1
DRVSS
PIN 1
2
IDENTIFIER
(LSB) D0
3
D1
4
D2
5
D3
AD9843A
6
D4
7
(Not to Scale)
D5
8
D6
9
D7
10
D8
11
(MSB) D9
12
10
13 14 15 16 17 18 19 20 21 22 23 24
3V
DRIVER
SUPPLY
0.1 F
0.1 F
ANALOG SUPPLY
Grounding and Decoupling Recommendations
As shown in Figure 17, a single ground plane is recommended
for the AD9843A. This ground plane should be as continu-
ous as possible, particularly around Pins 25 through 39. This
will ensure that all analog decoupling capacitors provide the lowest
possible impedance path between the power and bypass pins
and their respective ground pins. All decoupling capacitors
should be located as close as possible to the package pins. A
single clean power supply is recommended for the AD9843A,
but a separate digital driver supply may be used for DRVDD
(Pin 13). DRVDD should always be decoupled to DRVSS (Pin
14), which should be connected to the analog ground plane.
Advantages of using a separate digital driver supply include
using a lower voltage (2.7 V) to match levels with a 2.7 V ASIC,
reducing digital power dissipation, and reducing potential noise
coupling. If the digital outputs (Pins 3–12) must drive a load
larger than 20 pF, buffering is recommended to reduce digital
code transition noise. Alternatively, placing series resistors
close to the digital output pins may help reduce noise.
3V
ANALOG SUPPLY
0.1 F
1.0 F
1.0 F
0.1 F
43 42 41 40
39 38
37
AUX1IN
36
AVSS
35
AUX2IN
34
AVDD2
33
BYP4
32
NC
31
CCDIN
TOP VIEW
30
BYP2
29
BYP1
28
AVDD1
27
AVSS
26
AVSS
25
NC = NO CONNECT
6
CLOCK
INPUTS
3V
AD9843A
0.1 F
3V
ANALOG
SUPPLY
0.1 F
0.1 F
CCD
SIGNAL
0.1 F
3V
0.1 F
ANALOG
SUPPLY
0.1 F
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