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Serial
Communications
The CPU section operation is typical of any microcomputer:
1. The restart logic applies a RESET command to the processor when power is applied.
2. The processor then begins to execute the program stored at the RESET address, which is located
in the EPROM.
3. After the RESET routines have been executed, the processor executes the normal operating
program. This program monitors the PIAs and the ACIA, and controls the PTM. Based on the
information received, the processor sends the necessary control signals to the PIAs to operate the
pulldown, constant-velocity, and shutter motors.
A phase-locked loop, located on this card, locks the internal signals to an external 50- or 60-Hz source. The phase-locked
oscillator is U16. The PTM divides the oscillator output of 192 KHz to 60 Hz, and provides a 50% duty cycle to the
comparator of the phase-locked loop. The PTM divider is under software control, and can be adjusted to divide to 50 Hz
operation. U14, an EPLD, is a DRM that uses the phase-locked oscillator's output.
The 192 KHz signal input to the DRM can be multiplied by any value from .00 to .99. This function provides a precise
set of frequencies that are stepped from one value to another to ramp motors up and down in speed with linear and
consistent accelerations.
CHRISTIE INC. - 35/70 Service/PM Manual
CHRISTIE INC. -
July, 1997
Data, Address,
Control Bus
6809
CPU
PTM
ACIA
Figure 5.11: CPU Circuits
5 : T h e o r y o f O p e r a t i o n
Battery
27128
Backup
EPROM
RAM
Parallel
PIA
Communications
PIA
Communications
PIA
Communications
Parallel
Parallel
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