Interrupt Status Register - Advantech PCI-1730 User Manual

C.8

Interrupt Status Register

BASE+8H/CH/10H
The PCI-1730 Interrupt Status Register control the status of four interrupt signal
sources (IDI0, IDI1, DI0, DI1).
Table C-8 Register for Interrupt Status
Read
Bit #
BASE + 8H
BASE + CH
BASE + 10H
IDI/DInF
This bit is a flag indicating the status of an interrupt. User can read this bit to get the
status of the interrupt
0 No interrupt
1 Interrupt occurred
IDI/DInEN
0 Disable
1 Enable
IDI/DInRF
The interrupt can be triggered by a rising edge or falling edge of the interrupt signal,
as determined by the value in this bit.
0 Rising edge trigger
1 Falling edge trigger
The PCI-1733 Interrupt Status Register control the status of four interrupt signal
sources (IDI0, IDI1, IDI16, IDI17).
Table C-9 Register for Interrupt Status
Read
Bit #
BASE + 8H
BASE + CH
BASE + 10H
Interrupt Status Register
7 6 5
Interrupt flag bits (n = 0 ~ 1)
Interrupt enable control bits (n = 0 ~ 1)
Read this bit to Enable/Disable the interrupt.
Interrupt triggering control bits (n = 0 ~ 1)
Interrupt Status Register
7 6 5
4 3 2
DI1EN DI0EN
DI1RF DI0RF
DI1F DI0F
4 3 2
IDI17EN IDI16EN IDI1EN IDI0EN
IDI17RF IDI16RF IDI1RF IDI0RF
IDI17F IDI16F
43 PCI-1730/1733/1734 User Manual
1 0
IDI1EN IDI0EN
IDI1RF IDI0RF
IDI1F IDI0F
1 0
IDI1F IDI0F