Advantech PCI-1730 User Manual page 52

IDInF
This bit is a flag indicating the status of an interrupt. User can read this bit to get the
status of the interrupt
0 No interrupt
1 Interrupt occurred
IDInEN
0 Disable
1 Enable
IDInRF
The interrupt can be triggered by a rising edge or falling edge of the interrupt signal,
as determined by the value in this bit.
0 Rising edge trigger
1 Falling edge trigger
C.9 Interrupt Control Register — BASE+8H/CH/10H
The PCI-1730 Interrupt Control Register controls the status of four interrupt signal
sources (IDI0, IDI1, DI0, DI1). The user can clear the interrupt by writing its corre-
sponding value to the Interrupt Control Register, as shown in below table.
Table C-10 Register for Interrupt Control
Write
Bit #
BASE + 8H
BASE + CH
BASE + 10H
IDI/DInCLR
This bit must first be cleared to service the next interrupt.
0 Don't care
1 Clear the interrupt
IDI/DInEN
0 Disable
1 Enable
IDI/DInRF
The interrupt can be triggered by a rising edge or falling edge of the interrupt signal,
as determined by the value in this bit.
0 Rising edge trigger
1 Falling edge trigger
PCI-1730/1733/1734 User Manual
Interrupt flag bits (n = 0, 1, 16, 17)
Interrupt enable control bits (n = 0, 1, 16, 17)
Read this bit to Enable/Disable the interrupt.
Interrupt triggering control bits (n = 0, 1, 16, 17)
Interrupt Control Register
7 6 5
Interrupt clear control bits (n = 0 ~ 1)
Interrupt enable control bits (n = 0 ~ 1)
Read this bit to Enable/Disable the interrupt.
Interrupt triggering control bits (n = 0 ~ 1)
4 3 2
DI1EN DI0EN
DI1RF DI0RF
DI1CLR DI0CLR IDI1CLR IDI0CLR
44
1 0
IDI1EN IDI0EN
IDI1RF IDI0RF