Intel Xeon Datasheet page 41

Table 20. Signal Definitions (Sheet 3 of 9)
Name Type
BR0# I/O BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The BREQ[3:0]#
signals are interconnected in a rotating manner to individual processor pins. The tables
1
BR[1:3]# I
below provide the rotating interconnect between the processor and bus signals for 2-way
systems.
BR[1:0]# Signals Rotating Interconnect, 2-way sys
BR2# and BR3# must not be used in 2-way
platform designs. However, they must still be
terminated.
During power-on configuration, the central agent must assert the BR0# bus signal. All
symmetric agents sample their BR[3:0]# pins on the active-to-inactive transition of
RESET#. The pin which the agent samples asserted determines it's agent ID.
These signals do not have on-die termination and must be terminated at the end agent.
BSEL[1:0] O The BCLK[1:0] frequency select signals BSEL[1:0] are used to select the processor input
clock frequency.
frequency associated with each combination. The required frequency is determined by
the processors, chipset, and clock synthesizer. All front side bus agents must operate at
the same frequency. The Intel® Xeon™ processor with 800 MHz system bus currently
operates at a 800 MHz system bus frequency (200 MHz BCLK[1:0] frequency).
COMP[1:0] I COMP[1:0] must be terminated to V
inputs configure the GTL+ drivers of the processor.
D[63:0]# I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between
the processor front side bus agents, and must connect the appropriate pins on all such
agents. The data driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock
period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#.
Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#.
The following table shows the grouping of data signals to strobes and DBI#.
Furthermore, the DBI# pins determine the polarity of the data signals. Each group of 16
data signals corresponds to one DBI# signal. When the DBI# signal is active, the
corresponding data group is inverted and therefore sampled active high.
Datasheet
Bus Signal Agent 0 Pins
BREQ0# BR0#
BREQ1# BR1#
Table 3 defines the possible combinations of the signals and the
DSTBN#/
Data Group
DSTBP#
D[15:0]# 0
D[31:16]# 1
D[47:32]# 2
D[63:48]# 3
Intel® Xeon™ Processor with 800 MHz System Bus
Description
Agent 1 Pins
BR1#
BR0#
on the baseboard using precision resistors. These
SS
DBI#
0
1
2
3
Notes
1,4
4
41