Intel Xeon Datasheet page 24

Intel® Xeon™ Processor with 800 MHz System Bus
7. FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only. See
details on FMB guidelines.
8. This specification represents the V
9. This specification refers to the potential total reduction of the load line due to VID transitions below the specified VID.
10.V must be provided via a separate voltage source and must not be connected to V
TT
pin.
11. Baseboard bandwidth is limited to 20 MHz.
12.This specification refers to a single processor with R
I (max) simultaneously. This parameter is based on design characterization and not tested.
TT
13.This specification refers to a single processor with R
I (max) simultaneously. Details will be provided in future revisions of this document.
TT
14.These specifications apply to the PLL power pins VCCA, VCCIOPLL, and VSSA. See
parameters are based on design characterization and are not tested.
15.This specification represents a total current for all GTLREF pins.
16.The current specified is also for HALT State.
17.The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the
assertion of the PROCHOT# signal is the maximum I
18.I (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely
CC_TDC
and should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for monitoring its
temperature and asserting the necessary signal to inform the processor of a thermal excursion. Please see the applicable
design guidelines for further details. The processor is capable of drawing I
further details on the average processor current draw over various time durations. This parameter is based on design
characterization and is not tested.
19.This specification refers to platforms implementing a power delivery system that complies with VR 10.0 guidelines. Please see
the Voltage Regulator Module (VRM) and Enterprise Voltage-Regulator-Down (EVRD) 10.0 Design Guidelines for further
details.
20.This specification refers to platforms implementing a power delivery system that complies with VR 10.1 guidelines. Please see
the Voltage Regulator Module (VRM) and Enterprise Voltage-Regulator-Down (EVRD) 10.1 Design Guidelines for further
details.
24
reduction due to each VID transition. See
CC
enabled. Please note the end agent and middle agent may not require
TT
disabled. Please note the end agent and middle agent may not require
TT
for the processor.
CC
Section 2.11.1
Section 2.4.
. This specification is measured at the
CC
Section 2.3.2 for details. These
indefinitely. Refer to Figure 2
CC_TDC
for further
and Figure 3 for
Datasheet