Mps Version Control For Os; Advanced Chipset Features; Dram Timing Selectable; Cas Latency Time - Albatron PX915P4 Series User Manual

PX915P4/ PX915G4 Series

MPS Version Control For OS

The 1.1 version is the older version that supports 8 more IRQs in the Windows NT environment. Choose
the new 1.4 version for Windows 2000 and Windows XP.
Options: 1.4 (default)、1.1
OS Select For DRAM > 64MB
Select "OS2" only if you are running the OS/2 operating system with greater than 64MB of RAM. Options:
Non-OS2 (default)、OS2
HDD S.M.A.R.T. Capability
Self Monitoring Analysis and Reporting Technology is a technology that enables a PC to attempt to
predict the possible failure of storage drives.
Options: Disabled (default)、Enabled
Intel OSB Logo Show
This item allows you to show or hide the small LOGO EPA.
Options: Disabled、Enabled (default)

Advanced Chipset Features

DRAM Timing Selectable

This item determines DRAM clock/ timing using SPD or manual configuration.
Make sure your memory module has SPD (Serial Presence Data), if you want to select the "By SPD"
option. Options: Manual、By SPD (default)

CAS Latency Time

This item determines CAS Latency. When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from the default value specified by the
system engineer. This field is adjustable only when "DRAM Timing Selectable" is set to "Manual". This
field is locked when "DRAM Timing Selectable" is set to "By SPD" and is automatically determined by the
system. Options: 2、2.5、3
DRAM RAS# to CAS# Delay
This item allows you to select a delay time between the CAS and RAS strobe signals. It only applies
when DRAM is written to, read from, or refreshed. This field is adjustable only when "DRAM Timing
Selectable" is set to "manual". This field is locked when "DRAM Timing Selectable" is set to "By SPD"
and is automatically determined by the system.
Options: 4、3、2
DRAM RAS# Precharge
This item allows you to select the DRAM RAS# precharge time. The ROW address strobe must
precharge again before DRAM is refreshed. An inadequate configuration may result in incomplete data.
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