Pci To Isa Bus Interrupt Mapping; Pci Bus Configuration Space - Intergraph Rack-Mount Workstation/Server System Reference Manual

PCI to ISA Bus Interrupt Mapping

The ISA bridge (Intel 82379AB) or MSMT359 the sixteen conventional ISA interrupts, plus four
interrupt request pins for PCI peripheral interrupts (PIRQ0 through PIRQ3). For PC-AT architecture
compatibility reasons, the PCI interrupts are routed to the ISA interrupts within the ISA bridge. The
assertion of a PCI interrupt concludes in an ISA interrupt being asserted.
The 8-bit PIRQ Route Control Registers in the ISA bridge determine to which ISA interrupt a PIRQ
or MSMT359 is routed. Four PIRQ Route Control Registers are used for the PCI interrupts, located
at the ISA bridge address offsets defined below.
PCI Interrupt Request
PIRQ0
PIRQ1
PIRQ2
PIRQ3
Bit 7 of each PIRQ registers enable (Low) or disable (High) the routing of the PIRQ to an ISA
interrupt. The lowest four bits (3:0) of each PIRQ register determines to which ISA interrupt the
PIRQ will be routed, as defined below.
Bits (3:0) of PIRQ
0000
0001
0010
0011
0100
0101
0110
0111

PCI Bus Configuration Space

The table below lists the configuration space used for the primary PCI bus. The PCI bus uses type 1
configuration access, which specifies two 32-bit I/O ports used as the index register (0CF8h) and the
data register (0CFCh).
Device
Host-to-PCI Bridge (PCMC)
PCI-to-ISA Bridge
Graphics Accelerator
Ethernet Controller
SCSI Controller
PCI Slot 1
PCI Slot 2
PCI Slot 3
Address Offset (Hex)
60
61
62
63
ISA Interrupt Bits (3:0) of PIRQ
Reserved 1000
Reserved 1001
Reserved 1010
IRQ3 1011
IRQ4 1100
IRQ5 1101
IRQ6 1110
IRQ7 1111
Device Number
0
2
5
6
7
D
E
F
ISA Interrupt
Reserved
IRQ9
IRQ10
IRQ11
IRQ12
Reserved
IRQ14
IRQ15
0CF8h Value
800000XX
800010XX
800028XX
800030XX
800038XX
800068XX
800070XX
800078XX
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