Table of Contents
Advertisement
The processor implements two software interfaces for requesting extended package
low power states: MWAIT instruction extensions with sub-state hints and via BIOS by
configuring MSR bits to automatically promote package low power states to extended
package low power states.
Extended Stop-Grant and Extended Deeper Sleep must be enabled via the
BIOS for the processor to remain within specification. Any attempt to operate
the processor outside these operating limits may result in permanent damage to the
processor. As processor technology changes, enabling the extended low power states
becomes increasingly crucial when building computer systems. Maintaining the proper
BIOS configuration is key to reliable, long-term system operation. Not complying with
this guideline may affect the long-term reliability of the processor.
Enhanced Intel SpeedStep Technology transitions are multistep processes that require
clocked control. These transitions cannot occur when the processor is in the Sleep or
Deep Sleep package low power states since processor clocks are not active in these
states. Extended Deeper Sleep state configuration lowers core voltage to the Deeper
Sleep level while in Deeper Sleep and, upon exit, automatically transitions to the lowest
operating voltage and frequency to reduce snoop service latency. The transition to the
lowest operating point or back to the original software requested point may not be
instantaneous. Furthermore, upon very frequent transitions between active and idle
states, the transitions may lag behind the idle state entry resulting in the processor
either executing for a longer time at the lowest operating point or running idle at a high
operating point. Observations and analyses show this behavior should not significantly
impact total power savings or performance score while providing power benefits in
most other cases.
2.4
FSB Low Power Enhancements
The processor incorporates FSB low power enhancements:
• Dynamic FSB Power Down
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On Die Termination disabling
• Low V
The processor incorporates the DPWR# signal that controls the data bus input buffers
on the processor. The DPWR# signal disables the buffers when not used and activates
them only when data bus activity occurs, resulting in significant power savings with no
performance impact. BPRI# control also allows the processor address and control input
buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows
a reciprocal power reduction in chipset address and control input buffers when the
processor deasserts its BR0# pin. The On Die Termination on the processor FSB buffers
is disabled when the signals are driven low, resulting in additional power savings. The
low I/O termination voltage is on a dedicated voltage plane, independent of the core
voltage, enabling low I/O switching power at all times.
2.5
VID-x
The processor implements the VID-x feature when in Intel Dynamic
Acceleration Technology mode. VID-x provides the ability for the processor to
request core voltage level reductions greater than one VID tick. The quantity of VID
ticks to be reduced depends on the specific performance state in which the processor is
running. This improved voltage regulator efficiency during periods of reduced power
20
(I/O termination voltage)
CCP
Low Power Features
Datasheet
Advertisement
Table of Contents
