Intel BX80562QX6700 - Core 2 Extreme 2.66 GHz Processor Datasheet page 69

Land Listing and Signal Descriptions
Table 25. Signal Description (Sheet 8 of 9)
Name
THERMTRIP#
TMS
TRDY#
TRST#
VCC
VCCPLL
VCC_SENSE
VCC_MB_
REGULATION
VID[7:0]
VID_SELECT
Datasheet
Type
In the event of a catastrophic cooling failure, the processor will
automatically shut down when the silicon has reached a
temperature approximately 20 °C above the maximum T
of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond where permanent silicon
damage may occur. Upon assertion of THERMTRIP#, the processor
will shut off its internal clocks (thus, halting program execution) in
an attempt to reduce the processor junction temperature. To protect
the processor, its core voltage (V
Output assertion of THERMTRIP#. Driving of the THERMTRIP# signal is
enabled within 10 μs of the assertion of PWRGOOD (provided V
and V are valid) and is disabled on de-assertion of PWRGOOD (if
CC
V or V are not valid, THERMTRIP# may also be disabled). Once
TT CC
activated, THERMTRIP# remains latched until PWRGOOD, V
V is de-asserted. While the de-assertion of the PWRGOOD, V
CC
V will de-assert THERMTRIP#, if the processor's junction
CC
temperature remains at or above the trip level, THERMTRIP# will
again be asserted within 10 μs of the assertion of PWRGOOD
(provided V and V
TT
TMS (Test Mode Select) is a JTAG specification support signal used
Input
by debug tools.
TRDY# (Target Ready) is asserted by the target to indicate that it is
Input ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins/lands of all FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
Input
must be driven low during power on Reset.
VCC are the power pins for the processor. The voltage supplied to
Input
these pins is determined by the VID[7:0] pins.
Input VCCPLL provides isolated power for internal processor FSB PLLs.
VCC_SENSE is an isolated low impedance connection to processor
Output core power (V ). It can be used to sense or measure voltage near
CC
the silicon with little noise.
This land is provided as a voltage regulator feedback sense point for
V . It is connected internally in the processor package to the sense
CC
Output point land U27 as described in the Voltage Regulator-Down (VRD)
11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket.
VID[7:0] (Voltage ID) signals are used to support automatic
selection of power supply voltages (V
Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket for more information. The
voltage supply for these signals must be valid before the VR can
Output supply V to the processor. Conversely, the VR output must be
CC
disabled until the voltage supply for the VID signals becomes valid.
The VID signals are needed to support the processor voltage
specification variations. See
The VR must supply the voltage that is requested by the signals, or
disable itself.
This land is tied high on the processor package and is used by the
VR to choose the proper VID table. Refer to the Voltage Regulator-
Output
Down (VRD) 11.0 Processor Power Delivery Design Guidelines For
Desktop LGA775 Socket for more information.
Description
) must be removed following the
CC
are valid).
CC
). Refer to the Voltage
CC
Table 2 for definitions of these signals.
. Assertion
C
TT
, or
TT
, or
TT
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