AOpen AP5TC User Manual page 63

AWARD BIOS
Chipset Features à Memory Hole At 15M-16M
Memory Hole At
15M-16M
Enabled
Disabled
Chipset Features à PCI Passive Release
PCI Passive Release
Enabled
Disabled
Chipset Features à PCI Delayed Transaction
PCI Delayed
Transaction
Enabled
Disabled
Chipset Features à Mem. Drive Str. (MA/RAS)
Mem. Drive Str.
(MA/RAS)
10mA/10mA
10mA/16mA
16mA/10mA
16mA/16mA
3-16
This option lets you reserve system memory area for
special ISA cards. The chipset accesses code/data
of these areas from the ISA bus directly. Normally,
these areas are reserved for memory mapped I/O
card.
This item lets you control the Passive Release
function of the PIIX4 chipset (Intel PCI to ISA bridge).
This function is used to meet latency of ISA bus
master. Try to enable or disable it, if you have ISA
card compatibility problem.
This item lets you control the Delayed Transaction
function of the PIIX4 chipset (Intel PCI to ISA bridge).
This function is used to meet latency of PCI cycles to
or from ISA bus. Try to enable or disable it, if you
have ISA card compatibility problem.
This option controls the driving strength of memory
address and control signals. It is recommended to
use less driving current for light memory loading, to
prevent undershoot or overshoot.