AOpen AP5TC User Manual page 61

AWARD BIOS
Chipset Features à DRAM Page Idle Timer
DRAM Page Idle
Timer
2 Clks
4 Clks
6 Clks
8 Clks
Chipset Features à DRAM Enhance Paging
DRAM Enhance
Paging
Enabled
Disabled
Chipset Features à SDRAM (CAS Lat/RAS-to-CAS)
SDRAM(CAS
Lat/RAS-to-CAS)
2/2
3/3
Chipset Features à SDRAM Speculative Read
SDRAM Speculative
Read
Enabled
Disabled
Chipset Features à System BIOS Cacheable
System BIOS
Cacheable
Enabled
Disabled
3-14
This item determines the amount of time in CPU
clocks that DRAM page will be close after CPU
becomes idle.
When Enabled, TX chipset will keep DRAM page
open as long as possible according to enhanced
method.
These are timing of SDRAM CAS Latency and RAS
to CAS Delay, calculated by clocks. They are
important parameters affects SDRAM performance,
default is 2 clocks. If your SDRAM has unstable
problem, change 2/2 to 3/3.
Enable this item reduce one clock of SDRAM read
leadoff timing by presenting the SDRAM read request
before the controller chip decodes the final memory
target. This Item must be Disabled if more than one
DIMM is installed in the system.
Enabling this item allows you to cache the system
BIOS to further enhance system performance.