AOpen AP5TC User Manual page 43

Hardware Installation
Double side module at either Bank0 or
DIMM1, the other must be empty.
Following table explains more about the RAS limitation. You can see that Bank0
1st side and DIMM1 2nd side use the same RAS0#, and Bank0 2nd side and
DIMM1 1st side use the same RAS1#. If you are using single side SIMM at Bank0
and single side DIMM at DIMM1, it should be no problem. But only one double
side DIMM or double side SIMM can be at Bank0 or DIMM1.
Bank0
1st
side
RAS0#
X
RAS1#
RAS2#
RAS3#
Caution: Make sure that you install the same SIMM type and
size for each bank.
Caution: There are some old DIMMs made by EDO or FPM
memory chip, they can only accept 5V power and probably can
not fit into the DIMM socket, make sure you have 3.3V true
SDRAM DIMM before your insert it.
Tip: If you have DIMM made by 3V EDO, it is possible that TX
chipset can support it. But because it is so rare, the only 3V
EDO DIMM had been tested by this mainboard is Micron
MT4LC2M8E7DJ-6.
Warning: Do not use SIMM and SDRAM DIMM together unless
you have 5V tolerance SDRAM (such as Samsung or TI). The
FPM/EDO operate at 5V while SDRAM operates at 3.3V. If you
combine them together the system will temporary work fine;
however after a few months, the SDRAM 3.3V data input will be
damaged by 5V FPM/EDO data output line.
2-26
Bank0 Bank1
2nd 1st
side side
X
X
Double side module at either Bank1 or
DIMM2, the other must be empty.
Bank1 DIMM1
2nd 1st
side side
X
X
DIMM1 DIMM2
2nd 1st
side side
X
X
DIMM2
2nd
side
X