AOpen AP5TC User Manual page 44

There is an important parameter affects SDRAM performance, CAS Latency Time.
It is similar as CAS Access Time of EDO DRAM and is calculated as number of
clock state. The SDRAM that AOpen had tested are listed below. If your SDRAM
has unstable problem, go into BIOS "Chipset Features Setup", change CAS
Latency Time to 3 clocks.
Manufacturer
Samsung
NEC
Hitachi
Fujitsu
TI
TI
TI
TI
The driving capability of new generation chipset is limited because the lack of
memory buffer (to improve performance). This makes DRAM chip count an
important factor to be taking into consideration when you install SIMM/DIMM.
Unfortunately, there is no way that BIOS can identified the correct chip count, you
need to calculate the chip count by yourself. The simple rule is: By visual
inspection, use only SIMM with chip count less than 24 chips, and use only DIMM
which is less than 16 chips.
Warning: Do not install any SIMM that contains more than 24
chips. SIMMs contain more than 24 chips exceed the chipset
driving specification. Doing so may result in unstable system
behavior.
Warning: Although Intel TX chipset supports x4 SDRAM chip.
Due to loading issue, it is not recommended to use this kind of
SDRAM.
Tip: The SIMM/DIMM chip count can be calculated by following
example:
1. For 32 bit non-parity SIMM using 1M by 4 bit DRAM chip,
2. For 36 bit parity SIMM
3. For 36 bit parity SIMM using 1M by 4 bit and 1M by 1 bit
Model
KM416511220AT-G12
D4S16162G5-A12-7JF
HM5216805TT10
81117822A-100FN
TMX626812DGE-12
TMS626812DGE-15
TMS626162DGE-15
TMS626162DGE-M67
32/4=8 chips.
36/4=9 chips.
DRAM, the chip count will be 8 data chips(8= 32/4) plus 4
Hardware Installation
Suggested CAS
Latency Time
2
2
2
2
2
3
3
3
using 1M by 4 bit DRAM chip,
5V Tolerance
Yes
No
No
No
Yes
Yes
Yes
Yes
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