Texas Instruments ADS1282V2EVM-PDK User Manual page 24

Hardware Design Files
Flip-Flop for Sync
R57
DNP
0
DVDD
C30
0.1uF
U7
GND
14
VCC
OSC
3 5
1CLK 1Q
4 6
1PRE 1Q
SYNC_FFIN
2
1D
1
1CLR
11 9
2CLK 2Q
10 8
2PRE 2Q
12
2D
13 7
DVDD
2CLR GND
SN74HCS72PWR
Oscillator
DVDD
Y1
4
VDD
C32 R67
0.1uF 82k
3
ENABLE
2 1
OSC
OE
1
DISABLE
GND SiT1602BC -83-33E-4.096 000Y
JP3
GND
24 ADS1282EVM-PDK Evaluation Module
Optional pull-up resistors
SYNC
GND
R65
CLK
49.9
3
OUT
R66
OSC
0
2
GND
GND
Figure 5-3. ADS1282EVM Digital Interface & Clocking Schematic
Copyright © 2024 Texas Instruments Incorporated
Signal Bank
J7
~PWDN
1 2
~RESET
3 4
MFLAG
5 6
DVDD SYNC_FFIN
7 8
R58 10.0k SYNC
9 10
DNP
R59 10.0k M0
11 12
DNP
R60 10.0k M1
13 14
DNP
R61 10.0k MCLK
15 16
DNP
R62 10.0k DIN
17 18
DNP
DOUT
19 20
DRDY
21 22
SCLK
23 24
CAPCLK_OUT
25 26
OSC
27 28
GND
EVM GUI EEPROM EEPROM only used by PHI data
acquisition board; not needed in
end equipment design.
ID_PWR ID_PWR ID_PWR
C31
0.1uF
R64
10.0k
GND
U8
1 8
A0 VCC
2 7 WP
A1 WP
3 6 SCL
A2 SCL
4 5 SDA
VSS SDA
BR24G32FVT-3AGE2
GND GND
PHI Connector
J8
2
2
4
4
~PWDN
6
6
~RESET
8
8
MFLAG
10
10
SYNC_FFIN
12
12
M0
14
14
M1
16
16
DIN
18
18
MCLK
20
20
22
22
SCLK
24
24
CAPCLK_OUT
26
26
CAPCLK_IN
28
28
DRDY
30
30
OSC
32
32
34
34
36
36
DOUT
38
38
40
40
42
42
44
44
46
46
48
48
50
DVDD
50
52
52
54
54
SDA
56
56
SCL
58
58
60
60
MP1
GND
MP2
GND
QTH-030-01-L-D-A-K-TR
GND
1
2 Install jumper to disable
write protection
JP2
SBAU431 – JULY 2024
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5.5V
1
1
3
3
5
5
7
7
GND
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
R63
WP
49
49
51
49.9
51
53
53
55
55
57
57
59
ID_PWR
59
MP3
GND
MP4
GND
GND