Texas Instruments ADS1282V2EVM-PDK User Manual page 10

Hardware
2.9 Flip-Flop/SYNC Circuit
Figure 2-9 shows the flip-flop circuit used to synchronize the SYNC input. The SYNC input allows the ADS1282
to synchronize the operation to an external event. The circuit utilizes the SN74HCS72, which is a Schmitt-Trigger
input, negative-edge-triggered, D-type flip-flop (U7). The SYNC input is latched on a falling, edge of the clock,
and clocked out into the ADS1282 on the next falling edge of the clock.
SYNC_FFIN
2.10 Clocking
Figure 2-10 shows the different clocking circuit for the ADS1282EVM that is enabled or disabled by jumper JP3.
The default setting for jumper JP3 is the 2-3 position (ENABLE), which enables the local 4.096MHz oscillator
(Y1) on the ADS1282EVM. This clock is routed to the main clock input (CLK pin) of the ADS1282. The oscillator
also connects to the clock input of the flip-flop circuit for the SYNC input. A 49.9Ω series resistor is placed on
the clock output to reduce overshoot and ringing on clock transitions. Moving JP3 to the 1-2 position (DISABLE)
allows an external clock supplied on header J2 (not populated). Use a CMOS square-wave signal with an
amplitude equal to 3.3V (DVDD) and a frequency within the specified range
DVDD
GND
10 ADS1282EVM-PDK Evaluation Module
DVDD
C30
0.1uF
GND
14
OSC
3
4
2
1
11
10
12
13
DVDD
Figure 2-9. Flip-Flop Sync Circuit
J2
DNP
Disable oscillator (Y1) and install J2 to
apply external clock source
C32 R67
0.1uF 82k
3
ENABLE
2
OSC
1
DISABLE
JP3
GND
Figure 2-10. Clocking
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R57
DNP
0
U7
VCC
5
1CLK 1Q
6
1PRE 1Q
1D
1CLR
9
2CLK 2Q
8
2PRE 2Q
2D
7
2CLR GND
SN74HCS72PWR
GND
(Table
CLK
2
1
GND
R65
Y1
49.9
4 3
VDD OUT
R66
0
1 2
OE GND
SiT1602BC-83-33E-4.096000Y
GND
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SYNC
1-1) of the ADS1282.
CLK
OSC
SBAU431 – JULY 2024
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