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2.11 Serial Interface
Figure 2-11
shows the digital connections between the ADS1282 and the PHI. The ADS1282 uses SPI serial
communication in mode 0 (CPOL = 0, CPHA = 0) to configure the internal registers. The signal bank (J7)
provides test points for the ADS1282EVM digital signals.
DVDD
R58
R59
R60
Op
o nal pull-up resistors
¡
R61
R62
Figure 2-11. Connections to Digital Signals on PHI and Test Points
2.12 EEPROM
Figure 2-12
shows the EEPROM circuit the PHI uses to identify the EVM at power up. The EEPROM
communicates with the PHI over an I2C bus that is not shared with the ADS1282. This circuit is not required by
the ADS1282 for operation and is powered down when not used by the PHI.
ID_PWR
GND
SBAU431 – JULY 2024
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J7
~PWDN
1
~RESET
3
MFLAG
5
SYNC_FFIN
7
10.0k
SYNC
9
DNP
10.0k
M0
11
DNP
10.0k
M1
13
DNP
10.0k
MCLK
15
DNP
10.0k
DIN
17
DNP
DOUT
19
DRDY
21
SCLK
23
CAPCLK_OUT
25
OSC
27
ID_PWR
ID_PWR
C31
0.1uF
U8
GND
1
8
A0
VCC
2
7
A1
WP
SCL
3
6
A2
SCL
SDA
4
5
VSS
SDA
BR24G32FVT-3AGE2
Figure 2-12. EEPROM for EVM ID
Copyright © 2024 Texas Instruments Incorporated
~PWDN
~RESET
MFLAG
SYNC_FFIN
M0
M1
DIN
MCLK
2
4
SCLK
6
CAPCLK_OUT
8
CAPCLK_IN
10
DRDY
12
OSC
14
16
18
DOUT
20
22
24
26
28
DVDD
SDA
GND
SCL
GND
EEPROM only used by PHI data
acquisi on board; not needed in
end equipment design.
R64
10.0k
WP
1
Install jumper to disable
2
write protec
¡
JP2
GND
J8
2
1
2
1
4
3
4
3
6
5
6
5
8
7
8
7
10
9
10
9
12
11
12
11
14
13
14
13
16
15
16
15
18
17
18
17
20
19
20
19
22
21
22
21
24
23
24
23
26
25
26
25
28
27
28
27
30
29
30
29
32
31
32
31
34
33
34
33
36
35
36
35
38
37
38
37
40
39
40
39
42
41
42
41
44
43
44
43
46
45
46
45
48
47
48
47
50
49
50
49
52
51
52
51
54
53
54
53
56
55
56
55
58
57
58
57
60
59
60
59
MP1
MP3
GND
GND
MP2
MP4
GND
GND
QTH-030-01-L-D-A-K-TR
GND
o n
ADS1282EVM-PDK Evaluation Module
Hardware
5.5V
GND
R63
WP
49.9
ID_PWR
11
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