Texas Instruments ADS1282V2EVM-PDK User Manual page 22

Hardware Design Files
5 Hardware Design Files
This section contains the ADS1282EVM schematics, PCB layouts, and bill of materials (BOM).
5.1 Schematics
External Inputs
J1 J2
2 SYNC 2 CLK
DNP DNP
1 1
GND GND
Install J1 to sync conversions to an Disable oscillator (Y1) and install J2 to
external event apply external clock source
Analog Input 1
R3 R4
-AIN1
221 221
R5 C5
20.0k 1000pF
3
2
Vocm
1
J3 GND
R6
20.0k C7
1000pF
R7 R8
+AIN1
221 221
Remove R11 to disable voltage
reference
Analog Input 2
R28
1.00k
AVDD(5.3)
C15
0.1uF
AVSS
7
U3
R29
+AIN2 THS4551IDGKR
8
5
1.00k
V+
Vocm 2
VOCM
4
R32
V-
DNP 1
20.0k
3
2
Vocm
1
J5 AVSS
R35
GND DNP
20.0k
R36 R37
-AIN2
1.00k 1.00k
22 ADS1282EVM-PDK Evaluation Module
AINN1
C6
0.01µF
AVDD(5.3)
Voltage Reference
AINP1
C8
1µF
AVSS U2
1
VIN
R11
0
2
EN
3
SS
4
FILT
R21 R22 REF6050IDGKR
10.0k 120k C14
1µF
AVSS AVSS AVSS
R30 R31
AINN2
15 10
C18
0.01µF
R33 R34
AINP2
15 10
Figure 5-1. ADS1282EVM Analog Inputs & Reference Schematic
Copyright © 2024 Texas Instruments Incorporated
Remove R1 and R2 to measure
AVDD and DVDD supply currents
using external ammeter
AVDD(5.3)
R1
0
DVDD
TP1
R2
0
DVDD
Remove R12 and R18 to disconnect
REF6050 reference and then install
J4 to provide an external reference
J4
EXT_REF R9 and R13 are optional filter
Vref resistors when using external
DNP
Vref on J4
5
OUT_S
R12 0
6
OUT_F
R15
0.22
7
GND_F
C11
8 0.01uF
GND_S
C13 R18
22µF 0
AVSS AVSS
AVDD_pin
C1
C2
10µF
1µF
AVSS
DVDD_pin
C3 C4
10µF 1µF
GND
ADS1282
U1
19
AVDD CAPP
26
DVDD CAPN
R9
C10
22
0
VREFP RESET
0.01uF
R13
21
VREFN PWDN
0
28
BYPAS MCLK
C12 CLK
1
CLK M0
1µF
R19
SYNC SYNC_pin
10
SYNC M1
49.9
R23
DRDY 3
DRDY SCLK
GND
49.9
AINP1
17
AI NP1 DOUT
AINN1
18
AI NN1 DI N
AINP2 15
AI NP2 MFLAG
AINN2
16
AI NN2 AVSS
DGND
DGND
DGND
DGND
ADS1282IPWR
SBAU431 – JULY 2024
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C9
14 0.01uF
13
R10
~RESET
24
49.9
R14
~PWDN
23
49.9
R16
7 MCLK
49.9
R17
M0
9
49.9
R20
M1
8
49.9
R24
2 SCLK
49.9
R25
DOUT
4
49.9
R26
DIN
5
49.9
R27
11 MFLAG
49.9
AVSS
20
6
12
25
C16
27
C17 10µF
1µF
GND GND