Firefly Connector ﴾J1401/J1402; M.2 Socket ﴾J1400; J1400 - M.2 Specifications - Enclustra Mercury+ PE3 User Manual

The pinout on the HDMI connector corresponds to the HDMI standard. In order to transmit video signals
through the links, FPGA support is required ﴾video protocol implementation﴿.
This interface is protected against electrostatic discharge ﴾ESD﴿ by using TVS diodes.
4.13 Firefly Connector ﴾J1401/J1402﴿
By default, the Mercury+ PE3 base board supports ECUO, ETUO and ECUE Firefly modules with 4 RX/TX
pairs and up to 10 Gbit/s datarate.
Four additional FPGA I/O pairs are connected to the reserved ﴾RSVD﴿ pins of the Firefly connector ﴾J1401﴿.
These additional I/Os FF_DIO[0:3]_P/N are referenced to VCC_IO_A. Refer to the Mercury Master Pinout
[8] or the Mercury+ PE3 Base Board User Schematic [3] for details on these connections.
The Firefly TX and RX signals are routed to the MGT multiplexing circuit. Refer to Section
on MGT multiplexing options.
NOTICE
Damage due to unsuitable voltage of the FF_DIO[0:3]_P/N pins
The FF_DIO[0:3]_P/N pins are directly connected to the FPGA/SoC device. Unsuit‐
able voltages can lead to damage to the mounted FPGA/SoC module and other
devices on the base board.
4.14 M.2 Socket ﴾J1400﴿
The Mercury+ PE3 base board is equipped with a M.2 socket, which can be connected an MGT transceiver
via MGT multiplexer. See Section
addition, the module used in combination with the Mercury+ PE3 base board must also support the used
SSD.
Name Specification
Protocol SATA or NVMe
Key M or B&M Key
Length 2242, 2260 or 2280
Table 16: J1400 ‐ M.2 Specifications
The MGT transceiver may optionally be connected to an additional DisplayPort lane, instead of the M.2
socket. By default, the M.2 socket is connected to the MGT ﴾while DisplayPort supports a single lane﴿,
and as an assembly option M.2 socket may remain unused ﴾while DisplayPort can use two lanes﴿.
The polarity of M2_RX0 was chosen to fulfill SATA standard. For PCIe support lane polarity reversal must
be activated.
D‐0000‐420‐001
Ensure that the IO voltage of FF_DIO[0:3]_P/N does not exceed VCC_IO_A.
6.2 for details. Table 16 lists the specification of supported SSDs. In
26 / 63
6.2 for details
Version 03, 11.07.2024