Pin Definitions - Cypress CY14B101L Specification Sheet

Pinouts
V 1
CAP
A 2
16
A 3
14
A 4
12
A 5
7
A 6
6
A 7
5
A 8
4
A 9
3
A 10
2
A 11
1
A 12
0
DQ 13
0
DQ 14
1
15
DQ
2
16
V
SS

Pin Definitions

Pin Name Alt IO Type
A –A Input
0 16
DQ -DQ Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
0 7
Input
WE W
Input
CE E
Input
OE G
V Ground
SS
V Power Supply Power Supply Inputs to the Device.
CC
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
HSB
V Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
CAP
NC No Connect
Document Number: 001-06400 Rev. *I
Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP
32 V
CC
31 A
15
30 HSB
29 WE
28
A
13
27
A
8
26 A
9
25 A
11
24 OE
23 A
10
22
CE
21
DQ
7
20
DQ
6
19 DQ
5
18
DQ
4
17
DQ
3
Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM.
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground for the Device. The device is connected to ground of the system.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
to nonvolatile elements.
No Connect. This pin is not connected to the die.
V
1
CAP
2
A
16
3
A
14
A 4
12
5
A
7
A
6
6
A 7
5
NC 8
A 9
4
Top View
10
NC
(not to scale)
NC 11
12
NC
V 13
SS
14
NC
15
NC
DQ0 16
17
A
3
18
A
2
A 19
1
A 20
0
DQ1 21
DQ2 22
NC 23
24
NC
Description
CY14B101L
V
48
CC
A
47
15
46
HSB
45 WE
A
44
13
43 A
8
42 A
9
41 NC
40 A
11
39 NC
38 NC
NC
37
36 V
SS
NC
35
NC
34
DQ6
33
32 OE
A
31
10
CE
30
29 DQ7
28 DQ5
DQ4
27
26 DQ3
25 V
CC
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