Cypress CY14B104K Specification Sheet

4 mbit (512k x 8/256k x 16) nvsram with real time clock

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Features
20 ns, 25 ns, and 45 ns access times
Internally organized as 512K x 8 (CY14B104K) or 256K x 16
(CY14B104M)
Hands off automatic STORE on power down with only a small
capacitor
®
STORE to QuantumTrap
nonvolatile elements is initiated by
software, device pin, or AutoStore
RECALL to SRAM initiated by software or power up
High reliability
Infinite Read, Write, and RECALL cycles
200,000 STORE cycles to QuantumTrap
20 year data retention
Single 3V +20%, –10% operation
Data integrity of Cypress nvSRAM combined with full featured

Real Time Clock

Logic Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
17
A
18
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
Notes
1. Address A
- A
for x8 configuration and Address A
0
18
2. Data DQ
- DQ
for x8 configuration and Data DQ
0
7
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-07103 Rev. *K
PRELIMINARY
4 Mbit (512K x 8/256K x 16) nvSRAM with
®
on power down
[1, 2, 3]
R
O
W
D
E
STATIC RAM
C
ARRAY
O
2048 X 2048
D
E
R
I
N
P
U
T
B
COLUMN I/O
U
F
F
E
R
COLUMN DEC
S
A
A
A
A
9
10
11
12
- A
for x16 configuration.
0
17
- DQ
for x16 configuration.
0
15
198 Champion Court
CY14B104K, CY14B104M
Watchdog timer
Clock alarm with programmable interrupts
Capacitor or battery backup for RTC
Commercial and industrial temperatures
44 and 54-pin TSOP II package
Pb-free and RoHS compliance
Functional Description
The Cypress CY14B104K/CY14B104M combines a 4-Mbit
nonvolatile static RAM with a full featured Real Time Clock in a
monolithic integrated circuit. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world's most reliable nonvolatile memory. The SRAM is read and
written infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
The Real Time Clock function provides an accurate clock with
leap year tracking and a programmable, high accuracy oscillator.
The alarm function is programmable for periodic minutes, hours,
days or months alarms. There is also a programmable watchdog
timer for process control.
V
V
CA
Quatrum
CC
P
Trap
2048 X 2048
POWER
CONTROL
STORE
RECALL
STORE/RECALL
CONTROL
SOFTWARE
DETECT
A
A
A
A
13
14
15
16
,
San Jose
Real Time Clock
V
RTCbat
V
RTCcap
HSB
A
- A
14
2
RTC
MUX
A
CA 95134-1709
408-943-2600
Revised January 29, 2009
X
1
X
2
INT
- A
18
0
OE
WE
CE
BLE
BHE
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Summary of Contents for Cypress CY14B104K

  • Page 1: Real Time Clock

    Features 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104K) or 256K x 16 ■ (CY14B104M) Hands off automatic STORE on power down with only a small ■ capacitor ® STORE to QuantumTrap nonvolatile elements is initiated by ■...
  • Page 2 5. Address expansion for 16 Mbit. NC pin not connected to die. Document #: 001-07103 Rev. *K PRELIMINARY RTCcap RTCbat Description - DQ - DQ CY14B104K, CY14B104M 54 - TSOP II (x16) Top View (not to scale) RTCcap RTCbat is used.
  • Page 3: Device Operation

    Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements. Device Operation The CY14B104K/CY14B104M nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap cell.
  • Page 4 HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Hardware STORE (HSB) Operation The CY14B104K/CY14B104M provides the HSB pin to control and acknowledge the STORE operations. The HSB pin is used to request a Hardware STORE cycle. When the HSB pin is driven...
  • Page 5 A sequence of read operations is performed in a Notes 6. While there are 19 address lines on the CY14B104K (18 address lines on the CY14B104M), only the 13 address lines (A Rest of the address lines are don’t care.
  • Page 6: Data Protection

    CY14B104K/CY14B104M is in a write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after t active). This protects against inadvertent writes during power up or brown out conditions.
  • Page 7 ) falls below their respective minimum level, RTCcap RTCbat the oscillator may fail.The CY14B104K has the ability to detect oscillator failure when system power is restored. This is recorded in the OSCF (Oscillator Failed bit) of the flags register at the address 0x7FFF0.
  • Page 8: Power Monitor

    Watchdog Register Power Monitor The CY14B104K provides a power management scheme with power fail interrupt capability. It also controls the internal switch to backup power for the clock and protects the memory from low access. The power monitor is based on an internal band gap reference circuit that compares the V threshold.
  • Page 9 = 21 pF Note: The recommended values for C1 and C2 include board trace capacitance. Figure 5. Interrupt Block Diagram Driver CY14B104K, CY14B104M WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable PF - Power Fail Flag PFE - Power Fail Enable...
  • Page 10 Table 4. RTC Register Map Register CY14B104K CY14B104M 0x7FFFF 0x3FFFF 0x7FFFE 0x3FFFE 0x7FFFD 0x3FFFD 0x7FFFC 0x3FFFC 0x7FFFB 0x3FFFB 0x7FFFA 0x3FFFA 0x7FFF9 0x3FFF9 0x7FFF8 0x3FFF8 OSCEN 0x7FFF7 0x3FFF7 0x7FFF6 0x3FFF6 WIE (0) 0x7FFF5 0x3FFF5 M (1) 0x7FFF4 0x3FFF4 M (1) 0x7FFF3...
  • Page 11 10s Day of Month Time Keeping - Day Time Keeping - Hours 10s Hours Time Keeping - Minutes 10s Minutes Time Keeping - Seconds 10s Seconds CY14B104K, CY14B104M Years Months Day of Month Day of Week Hours Minutes Seconds Page 11 of 31...
  • Page 12 Document #: 001-07103 Rev. *K PRELIMINARY Description Calibration/Control Calibration Sign WatchDog Timer Interrupt Status/Control Alarm - Day 10s Alarm Date CY14B104K, CY14B104M Calibration Watchdog Timer on page 7. Alarm Date Page 12 of 31 [+] Feedback...
  • Page 13 10s Alarm Seconds Time Keeping - Centuries 10s Centuries Flags OSCF . It is cleared to 0 when the Flags register is read or on power up. CY14B104K, CY14B104M Alarm Hours Alarm Minutes Alarm Seconds Centuries Page 13 of 31...
  • Page 14: Maximum Ratings

    < V < V , CE or OE > V = –2 mA = 4 mA pin and V , 5V Rated CY14B104K, CY14B104M + 2.0V = 25°C) ... 1.0W Ambient Temperature 0°C to +70°C 2.7V to 3.6V –40°C to +85°C 2.7V to 3.6V...
  • Page 15: Thermal Resistance

    Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. Figure 6. AC Test Loads 577Ω 3.0V OUTPUT 789Ω CY14B104K, CY14B104M Unit Years Unit 44 TSOP II 54 TSOP II Unit °C/W 31.11 30.73 °C/W...
  • Page 16 RTC Capacitor Pin Voltage RTCcap tOCS RTC Oscillator Time to Start Notes 15. From either V or V RTCcap RTCbat. Document #: 001-07103 Rev. *K PRELIMINARY Test Conditions Room Temperature (25 Hot Temperature (85 CY14B104K, CY14B104M Units Page 16 of 31 [+] Feedback...
  • Page 17: Switching Waveforms

    20. HSB must remain HIGH during READ and WRITE cycles. Document #: 001-07103 Rev. *K PRELIMINARY 20 ns Description [16, 17, 20] Address Valid CY14B104K, CY14B104M 25 ns 45 ns Unit Output Data Valid Page 17 of 31 [+] Feedback...
  • Page 18 Document #: 001-07103 Rev. *K PRELIMINARY [3, 16, 20] Address Valid LZCE LZOE LZBE Output Data Valid Active [3, 19, 20, 21] Address Valid Input Data Valid LZWE HZWE High Impedance CY14B104K, CY14B104M HZCE HZOE HZBE Page 18 of 31 [+] Feedback...
  • Page 19 22. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register. Document #: 001-07103 Rev. *K PRELIMINARY [3, 19, 20, 21] Address Valid Input Data Valid High Impedance Address Valid Input Data Valid High Impedance CY14B104K, CY14B104M [6, 19, 20, 21, 22] Page 19 of 31 [+] Feedback...
  • Page 20 Figure 12. AutoStore or Power Up RECALL Note STORE HHHD LZHSB DELAY HRECALL Read & Write BROWN POWER-UP RECALL Autostore SWITCH. SWITCH. CY14B104K, CY14B104M 25 ns 45 ns 2.65 2.65 [26] Note STORE Note HHHD DELAY LZHSB HRECALL Read & Write...
  • Page 21 Address #6 DELAY HZCE Figure 14. Autostore Enable and Disable Cycle Address #6 HZCE DELAY Table 1. WE must be HIGH during all six consecutive cycles. CY14B104K, CY14B104M [28, 29] 25 ns 45 ns [29] HHHD LZHSB High Impedance STORE...
  • Page 22 SRAM is disabled as long as HSB (IN) is driven low. DHSB DHSB [32, 33] Figure 16. Soft Sequence Processing Soft Sequence Command Address #6 Address #1 CY14B104K, CY14B104M 25 ns 45 ns Unit HHHD LZHSB only by Internal Address #6 Page 22 of 31...
  • Page 23 High-Z Output Disabled Data In (DQ –DQ Write Data In (DQ –DQ Write –DQ in High-Z Data In (DQ –DQ Write –DQ in High-Z CY14B104K, CY14B104M Mode Power Standby Active Active Active Mode Power Standby Active Active Active Active Active...
  • Page 24: Part Numbering Nomenclature

    C - Commercial (0 to 70°C) I - Industrial (–40 to 85°C) Pb-Free Package: ZS - TSOP II Voltage: B - 3.0V CY14B104K, CY14B104M Speed: 20 - 20 ns 25 - 25 ns 45 - 45 ns Data Bus: K - x8 + RTC...
  • Page 25: Ordering Information

    44-pin TSOPII 51-85087 44-pin TSOPII 51-85087 44-pin TSOPII 51-85187 44-pin TSOPII 51-85160 54-pin TSOPII 51-85160 54-pin TSOPII 51-85160 54-pin TSOPII 51-85160 54-pin TSOPII CY14B104K, CY14B104M Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Page 25 of 31...
  • Page 26: Package Diagrams

    Figure 17. 44-Pin TSOP II (51-85087) PIN 1 I.D. BASE PLANE 0°-5° 0.10 (.004) 0.597 (0.0235) 0.406 (0.0160) SEATING PLANE CY14B104K, CY14B104M DIMENSION IN MM (INCH) MIN. EJECTOR PIN BOTTOM VIEW 10.262 (0.404) 10.058 (0.396) 0.210 (0.0083) 0.120 (0.0047) 51-85087 *A...
  • Page 27 PRELIMINARY CY14B104K, CY14B104M Package Diagrams (continued) Figure 18. 54-Pin TSOP II (51-85160) 51-85160 ** Document #: 001-07103 Rev. *K Page 27 of 31 [+] Feedback...
  • Page 28 Document History Page Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 Submission Orig. of Rev. ECN No. Date Change 431039 See ECN 489096 See ECN 499597 See ECN 517793 See ECN...
  • Page 29 Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 ECN No. Submission Orig. of Rev. Date Change 1890926 See ECN vsutmp8/AE- 2267286 See ECN GVCH/PYRS Rearranging of “Features” 2483627 See ECN GVCH/PYRS Removed 8 mA typical I Document #: 001-07103 Rev.
  • Page 30 Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 ECN No. Submission Orig. of Rev. Date Change 2519319 06/20/08 GVCH/PYRS Added 20 ns access speed in “Features” 2600941 11/04/08 GVCH/PYRS Removed 15 ns access speed from “Features”...
  • Page 31 Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 Submission Orig. of Rev. ECN No. Date Change 2653928 02/04/09 GVCH/PYRS Changed Part number from CY14B104KA/CY14B104MA to Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors.

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