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Features
■
15 ns, 20 ns, 25 ns, and 45 ns access times
■
Internally organized as 256K x 8 (CY14E102L) or 128K x 16
(CY14E102N)
■
Hands off automatic STORE on power down with only a small
capacitor
™
■
STORE to QuantumTrap
software, device pin, or AutoStore
■
RECALL to SRAM initiated by software or power up
■
Infinite read, write, and recall cycles
■
200,000 STORE cycles to QuantumTrap
■
20 year data retention
■
Single 5V +10% operation
■
Commercial and Industrial temperatures
■
48-pin FBGA, 44 and 54-pin TSOP II packages
■
Pb-free and RoHS compliance
Logic Block Diagram
Address
Note
1. Address A
- A
and Data DQ0 - DQ7 for x8 configuration, Address A
0
17
Cypress Semiconductor Corporation
Document Number: 001-45755 Rev. *A
ADVANCE
2-Mbit (256K x 8/128K x 16) nvSRAM
nonvolatile elements initiated by
™
on power down
V
CC
[1]
A
- A
0
17
CE
OE
WE
BHE
BLE
V
•
198 Champion Court
Functional Description
The Cypress CY14E102L/CY14E102N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 256K words of 8 bits each or 128K words of 16 bits
each.
The
embedded
QuantumTrap technology, producing the world's most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data reside in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
V
CAP
CY14E102L
CY14E102N
SS
- A
and Data DQ0 - DQ15 for x16 configuration.
0
16
•
San Jose
CY14E102L, CY14E102N
nonvolatile
elements
[1]
DQ0 - DQ7
HSB
,
CA 95134-1709
•
408-943-2600
Revised June 27, 2008
incorporate
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Related Manuals for Cypress CY14E102L
Summary of Contents for Cypress CY14E102L
-
Page 1: Functional Description
Features ■ 15 ns, 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 256K x 8 (CY14E102L) or 128K x 16 (CY14E102N) ■ Hands off automatic STORE on power down with only a small capacitor ™... - Page 2 Document Number: 001-45755 Rev. *A ADVANCE Figure 1. Pin Diagram - 48 FBGA (Top View) DQ14 DQ15 Figure 2. Pin Diagram - 44 TSOP II (Top View) (Not to Scale) CY14E102L, CY14E102N (x16) (Not to Scale) DQ10 DQ11 DQ12 DQ13...
-
Page 3: Pin Definitions
No Connect No Connect. Do not connect this pin to the die. Document Number: 001-45755 Rev. *A ADVANCE Figure 3. Pin Diagram - 54 TSOP II (Top View) DQ15 DQ14 DQ13 (x16) DQ12 (Not to Scale) DQ11 DQ10 Description CY14E102L, CY14E102N Page 3 of 21 [+] Feedback... -
Page 4: Device Operation
Device Operation The CY14E102L/CY14E102N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data... - Page 5 5. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. 6. While there are 18/17 address lines on the CY14E102L/CY14E102N, only the lower 16 lines are used to control software modes.
-
Page 6: Data Protection
AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled. Data Protection The CY14E102L/CY14E102N protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is... -
Page 7: Maximum Ratings
< V , CE or OE > V = –2 mA = 4 mA pin and V , 5V Rated CY14E102L, CY14E102N = 25°C) ... 1.0W ... 15 mA Ambient Temperature 0°C to +70°C 4.5V to 5.5V –40°C to +85°C 4.5V to 5.5V... -
Page 8: Ac Test Conditions
11. These parameters are guaranteed but not tested. Document Number: 001-45755 Rev. *A ADVANCE [11] Test Conditions = 0 to 3.0V [11] Test Conditions 5.0V OUTPUT 512Ω CY14E102L, CY14E102N Unit 48-FBGA 44-TSOP II 54-TSOP II Unit 28.82 31.11 30.73 7.84 5.56 6.08 963Ω for tri-state specs 5 pF 512Ω... - Page 9 13. Device is continuously selected with CE and OE both LOW. 14. Measured ±200 mV from steady state output voltage. 15. If WE is LOW when CE goes LOW, the output goes into high impedance state. Document Number: 001-45755 Rev. *A CY14E102L, CY14E102N ADVANCE 15 ns 20 ns...
- Page 10 22. On a hardware STORE initiation, SRAM operation continues to be enabled for time t Document Number: 001-45755 Rev. *A ADVANCE 15ns 20 ns SWITCH. to allow read and write cycles to complete. DELAY CY14E102L, CY14E102N CY14E102L/CY14E102N Unit [18, 19] 25ns 45ns Unit CY14E102L/CY14E102N...
- Page 11 25. BHE and BLE are applicable for x16 configuration only. Document Number: 001-45755 Rev. *A ADVANCE DATA VALID LZCE LZOE LZBE ACTIVE CY14E102L, CY14E102N [12, 13, 23] [12, 23, 25] HZCE HZOE HZCE HZBE DATA VALID Page 11 of 21...
- Page 12 PREVIOUS DATA Figure 8. SRAM Write Cycle #2: CE Controlled ADDRESS BHE , BLE DATA IN DATA OUT Document Number: 001-45755 Rev. *A CY14E102L, CY14E102N ADVANCE [13, 21, 22, 23] DATA VALID HZWE HIGH IMPEDANCE [13, 21, 22, 23] DATA VALID...
- Page 13 26. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V Document Number: 001-45755 Rev. *A ADVANCE Figure 9. AutoStore or Power Up RECALL STORE HRECALL SWITCH CY14E102L, CY14E102N [26] STORE occurs only No STORE occurs if a SRAM write without atleast one SRAM write...
- Page 14 DATA VALID Document Number: 001-45755 Rev. *A ADVANCE ADDRESS # 6 GHAX DATA VALID Figure 12. Hardware STORE Cycle Figure 13. Soft Sequence Processing CY14E102L, CY14E102N [19] STORE RECALL HIGH IMPEDANCE [22] [20, 21] Page 14 of 21 [+] Feedback...
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Page 15: Ordering Information
CY14E102L-BA20XCT CY14E102L-BA20XIT CY14E102L-BA20XI CY14E102L-ZSP20XCT CY14E102L-ZSP20XIT CY14E102L-ZSP20XI CY14E102N-BA20XCT CY14E102N-BA20XIT CY14E102N-BA20XI CY14E102N-ZSP20XCT CY14E102N-ZSP20XIT CY14E102N-ZSP20XI Document Number: 001-45755 Rev. *A CY14E102L, CY14E102N ADVANCE Package Package Type Diagram 51-85087 44-pin TSOP II 51-85087 44-pin TSOP II 51-85087 44-pin TSOP II 51-85128 48-ball FBGA 51-85128... - Page 16 CY14E102N-BA45XI CY14E102N-ZSP45XCT CY14E102N-ZSP45XIT CY14E102N-ZSP45XI All parts are Pb-free. The above table contains Advance information. Please contact your local Cypress sales representative for availability of these parts. Document Number: 001-45755 Rev. *A CY14E102L, CY14E102N ADVANCE Package Package Type Diagram 51-85087 44-pin TSOP II...
-
Page 17: Part Numbering Nomenclature
P - 54 Pin Blank - 44 Pin NVSRAM 14 - Auto Store + Software Store + Hardware Store Cypress Document Number: 001-45755 Rev. *A CY14E102L, CY14E102N ADVANCE Option: T - Tape & Reel Temperature: Blank - Std. C - Commercial (0 to 70°C) I - Industrial (–40 to 85°C) -
Page 18: Package Diagrams
ADVANCE Figure 14. 44-Pin TSOP II PIN 1 I.D. BASE PLANE 0°-5° 0.10 (.004) 0.597 (0.0235) 0.406 (0.0160) SEATING PLANE CY14E102L, CY14E102N DIMENSION IN MM (INCH) MIN. EJECTOR PIN BOTTOM VIEW 10.262 (0.404) 10.058 (0.396) 0.210 (0.0083) 0.120 (0.0047) 51-85087-*A... - Page 19 Figure 15. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm TOP VIEW A1 CORNER 6.00±0.10 SEATING PLANE Document Number: 001-45755 Rev. *A CY14E102L, CY14E102N ADVANCE 0.15(4X) BOTTOM VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X)
- Page 20 CY14E102L, CY14E102N ADVANCE Package Diagrams (continued) Figure 16. 54-Pin TSOP II 51-85160-** Document Number: 001-45755 Rev. *A Page 20 of 21 [+] Feedback...
- Page 21 Document History Page Document Title: CY14E102L/CY14E102N 2-Mbit (256K x 8/128K x 16) nvSRAM Document Number: 001- 45755 Orig. of Submission REV. ECN NO. Change Date 2470086 GVCH 2522209 GVCH/ 06/27/2008 AESA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors.
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