Cypress CY14B101L Specification Sheet page 10

SRAM Write Cycle
Parameter
Cypress
Alt
Parameter
t t
WC AVAV
t t t
PWE WLWH, WLEH
t t t
SCE ELWH, ELEH
t t t
SD DVWH, DVEH
t t t
HD WHDX, EHDX
t t t
AW AVWH, AVEH
t t t
SA AVWL, AVEL
t t t
HA WHAX, EHAX
[9,11]
t t
HZWE WLQZ
[9]
t t
LZWE WHQX
Switching Waveforms
ADDRESS
CE
WE
DATA IN
DATA OUT
ADDRESS
CE
WE
DATA IN
DATA OUT
Notes
11. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
12. CE or WE must be greater than V
Document Number: 001-06400 Rev. *I
Description
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
Figure 7. SRAM Write Cycle 1: WE Controlled
t
SA
PREVIOUS DATA
Figure 8. SRAM Write Cycle 2: CE and OE Controlled
t
SA
t
AW
t
HIGH IMPEDANCE
during address transitions.
IH
25 ns
Min Max
25
20
20
10
0
20
0
0
10
3
[11, 12]
t
WC
t
SCE
t
AW
t
PWE
t
SD
DATA VALID
t
HZWE
HIGH IMPEDANCE
t
WC
t
SCE
PWE
t
SD
DATA VALID
CY14B101L
35 ns 45 ns
Min Max Min Max
35 45
25 30
25 30
12 15
0 0
25 30
0 0
0 0
13
3 3
t
HA
t
HD
t
LZWE
[11, 12]
t
HA
t
HD
Page 10 of 18
Unit
ns
ns
ns
ns
ns
ns
ns
ns
15 ns
ns
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