Switching Waveforms - Cypress CY14B101L Specification Sheet

AC Switching Characteristics
SRAM Read Cycle
Parameter
Cypress
Alt
Parameter
t t
ACE ELQV
[7]
t t t
RC AVAV, ELEH
[8]
t t
AA AVQV
t t
DOE GLQV
[8]
t t
OHA AXQX
[9]
t t
LZCE ELQX
[9]
t t
HZCE EHQZ
[9]
t t
LZOE GLQX
[9]
t t
HZOE GHQZ
[6]
t t
PU ELICCH
[6]
t t
PD EHICCL

Switching Waveforms

Notes
7. WE and HSB must be HIGH during SRAM READ cycles.
8. Device is continuously selected with CE and OE both Low.
9. Measured ±200 mV from steady state output voltage.
10. HSB must remain high during READ and WRITE cycles.
Document Number: 001-06400 Rev. *I
Description
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Figure 5. SRAM Read Cycle 1: Address Controlled
Figure 6. SRAM Read Cycle 2: CE and OE Controlled
25 ns 35 ns
Min Max Min Max
25 35
25 35
25 35
12 15
3 3
3 3
10 13
0 0
10 13
0 0
25 35
[7, 8, 10]
[7, 10]
CY14B101L
45 ns
Unit
Min Max
45 ns
45 ns
45 ns
20 ns
3 ns
3 ns
15 ns
0 ns
15 ns
0 ns
45 ns
Page 9 of 18
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