Cypress CY14B101L Specification Sheet page 6

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Table 1. Hardware Mode Selection
CE WE
H X
L H
L L
L H
L H
L H
L H
Notes
1. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes.
3. IO state depends on the state of OE. The IO table shown is based on OE Low.
Document Number: 001-06400 Rev. *I
A – A
OE
15 0
X X
L X
X X
L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Mode IO
Not Selected Output High Z
Read SRAM Output Data
Write SRAM Input Data
Read SRAM Output Data
Read SRAM Output Data
Read SRAM Output Data
Read SRAM Output Data
Read SRAM Output Data
AutoStore Disable Output Data
Read SRAM Output Data
Read SRAM Output Data
Read SRAM Output Data
Read SRAM Output Data
Read SRAM Output Data
AutoStore Enable Output Data
Read SRAM Output Data
Read SRAM Output Data
Read SRAM Output Data
Read SRAM Output Data
Read SRAM Output Data
Nonvolatile Store Output High Z
Read SRAM Output Data
Read SRAM Output Data
Read SRAM Output Data
Read SRAM Output Data
Read SRAM Output Data
Nonvolatile Recall Output High Z
CY14B101L
Power
Standby
[3]
Active
Active
[1, 2, 3]
Active
[1, 2, 3]
Active
[1, 2, 3]
Active I
CC2
[1, 2, 3]
Active
Page 6 of 18
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